test/MC/AArch64/SVE/fdivr-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3
   4 // ------------------------------------------------------------------------- //
   5 // Tied operands must match
   6
   7 fdivr    z0.h, p7/m, z1.h, z31.h
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
   9 // CHECK-NEXT: fdivr    z0.h, p7/m, z1.h, z31.h
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12
  13 // ------------------------------------------------------------------------- //
  14 // Invalid element widths.
  15
  16 fdivr    z0.b, p7/m, z0.b, z31.b
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  18 // CHECK-NEXT: fdivr    z0.b, p7/m, z0.b, z31.b
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 fdivr    z0.h, p7/m, z0.h, z31.s
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  23 // CHECK-NEXT: fdivr    z0.h, p7/m, z0.h, z31.s
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26
  27 // ------------------------------------------------------------------------- //
  28 // Invalid predicate
  29
  30 fdivr    z0.h, p8/m, z0.h, z31.h
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  32 // CHECK-NEXT: fdivr    z0.h, p8/m, z0.h, z31.h
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: