test/MC/AArch64/SVE/fsub-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // Invalid immediates (must be 0.5 or 1.0)
   5
   6 fsub z0.h, p0/m, z0.h, #0.0
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
   8 // CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.0
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fsub z0.h, p0/m, z0.h, #0.4999999999999999999999999
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
  13 // CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.4999999999999999999999999
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 fsub z0.h, p0/m, z0.h, #0.5000000000000000000000001
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
  18 // CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.5000000000000000000000001
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 fsub z0.h, p0/m, z0.h, #1.0000000000000000000000001
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
  23 // CHECK-NEXT: fsub z0.h, p0/m, z0.h, #1.0000000000000000000000001
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 fsub z0.h, p0/m, z0.h, #0.9999999999999999999999999
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid floating point constant, expected 0.5 or 1.0.
  28 // CHECK-NEXT: fsub z0.h, p0/m, z0.h, #0.9999999999999999999999999
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31
  32 // ------------------------------------------------------------------------- //
  33 // Tied operands must match
  34
  35 fsub    z0.h, p7/m, z1.h, z31.h
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
  37 // CHECK-NEXT: fsub    z0.h, p7/m, z1.h, z31.h
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40
  41 // ------------------------------------------------------------------------- //
  42 // Invalid element widths.
  43
  44 fsub    z0.b, p7/m, z0.b, z31.b
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  46 // CHECK-NEXT: fsub    z0.b, p7/m, z0.b, z31.b
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 fsub    z0.h, p7/m, z0.h, z31.s
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  51 // CHECK-NEXT: fsub    z0.h, p7/m, z0.h, z31.s
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 fsub z0.b, z1.b, z2.b
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  56 // CHECK-NEXT: fsub z0.b, z1.b, z2.b
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 fsub z0.h, z1.s, z2.s
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  61 // CHECK-NEXT: fsub z0.h, z1.s, z2.s
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 // ------------------------------------------------------------------------- //
  65 // Invalid predicate
  66
  67 fsub    z0.h, p8/m, z0.h, z31.h
  68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  69 // CHECK-NEXT: fsub    z0.h, p8/m, z0.h, z31.h
  70 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  71
  72
  73 // --------------------------------------------------------------------------//
  74 // Negative tests for instructions that are incompatible with movprfx
  75
  76 movprfx z0.d, p0/z, z7.d
  77 fsub z0.d, z1.d, z31.d
  78 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  79 // CHECK-NEXT: fsub z0.d, z1.d, z31.d
  80 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  81
  82 movprfx z0, z7
  83 fsub z0.d, z1.d, z31.d
  84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  85 // CHECK-NEXT: fsub z0.d, z1.d, z31.d
  86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: