test/MC/AArch64/SVE/ld1h-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Immediate out of lower bound [-8, 7].
   5
   6 ld1h z21.h, p4/z, [x17, #-9, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
   8 // CHECK-NEXT: ld1h z21.h, p4/z, [x17, #-9, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ld1h z10.h, p5/z, [x16, #8, MUL VL]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  13 // CHECK-NEXT: ld1h z10.h, p5/z, [x16, #8, MUL VL]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 ld1h z30.s, p6/z, [x25, #-9, MUL VL]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  18 // CHECK-NEXT: ld1h z30.s, p6/z, [x25, #-9, MUL VL]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 ld1h z29.s, p5/z, [x15, #8, MUL VL]
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  23 // CHECK-NEXT: ld1h z29.s, p5/z, [x15, #8, MUL VL]
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 ld1h z28.d, p2/z, [x28, #-9, MUL VL]
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  28 // CHECK-NEXT: ld1h z28.d, p2/z, [x28, #-9, MUL VL]
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 ld1h z27.d, p1/z, [x26, #8, MUL VL]
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  33 // CHECK-NEXT: ld1h z27.d, p1/z, [x26, #8, MUL VL]
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36
  37 // --------------------------------------------------------------------------//
  38 // restricted predicate has range [0, 7].
  39
  40 ld1h z9.h, p8/z, [x25, #1, MUL VL]
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  42 // CHECK-NEXT: ld1h z9.h, p8/z, [x25, #1, MUL VL]
  43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  44
  45 ld1h z12.s, p8/z, [x13, #1, MUL VL]
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  47 // CHECK-NEXT: ld1h z12.s, p8/z, [x13, #1, MUL VL]
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 ld1h z4.d, p8/z, [x11, #1, MUL VL]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  52 // CHECK-NEXT: ld1h z4.d, p8/z, [x11, #1, MUL VL]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55
  56 // --------------------------------------------------------------------------//
  57 // Invalid vector list.
  58
  59 ld1h { }, p0/z, [x1, #1, MUL VL]
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  61 // CHECK-NEXT: ld1h { }, p0/z, [x1, #1, MUL VL]
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  66 // CHECK-NEXT: ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69 ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  71 // CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74
  75 // --------------------------------------------------------------------------//
  76 // Invalid scalar + scalar addressing modes
  77
  78 ld1h z0.h, p0/z, [x0, x0]
  79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  80 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0]
  81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  82
  83 ld1h z0.h, p0/z, [x0, xzr]
  84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  85 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr]
  86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  87
  88 ld1h z0.h, p0/z, [x0, x0, lsl #2]
  89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  90 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2]
  91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  92
  93 ld1h z0.h, p0/z, [x0, w0]
  94 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  95 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0]
  96 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  97
  98 ld1h z0.h, p0/z, [x0, w0, uxtw]
  99 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 100 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
 101 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 102
 103
 104 // --------------------------------------------------------------------------//
 105 // Invalid scalar + vector addressing modes
 106
 107 ld1h z0.d, p0/z, [x0, z0.h]
 108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 109 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h]
 110 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 111
 112 ld1h z0.d, p0/z, [x0, z0.s]
 113 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 114 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s]
 115 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 116
 117 ld1h z0.s, p0/z, [x0, z0.s]
 118 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 119 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s]
 120 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 121
 122 ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
 123 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 124 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
 125 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 126
 127 ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
 128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 129 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
 130 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 131
 132 ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
 133 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 134 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
 135 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 136
 137 ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 138 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
 139 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 140 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 141
 142
 143 // --------------------------------------------------------------------------//
 144 // Invalid vector + immediate addressing modes
 145
 146 ld1h z0.s, p0/z, [z0.s, #-2]
 147 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 148 // CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-2]
 149 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 150
 151 ld1h z0.s, p0/z, [z0.s, #-1]
 152 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 153 // CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-1]
 154 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 155
 156 ld1h z0.s, p0/z, [z0.s, #63]
 157 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 158 // CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #63]
 159 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 160
 161 ld1h z0.s, p0/z, [z0.s, #64]
 162 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 163 // CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #64]
 164 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 165
 166 ld1h z0.s, p0/z, [z0.s, #3]
 167 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 168 // CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #3]
 169 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 170
 171 ld1h z0.d, p0/z, [z0.d, #-2]
 172 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 173 // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-2]
 174 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 175
 176 ld1h z0.d, p0/z, [z0.d, #-1]
 177 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 178 // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-1]
 179 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 180
 181 ld1h z0.d, p0/z, [z0.d, #63]
 182 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 183 // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #63]
 184 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 185
 186 ld1h z0.d, p0/z, [z0.d, #64]
 187 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 188 // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #64]
 189 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 190
 191 ld1h z0.d, p0/z, [z0.d, #3]
 192 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 193 // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3]
 194 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 195
 196
 197 // --------------------------------------------------------------------------//
 198 // Negative tests for instructions that are incompatible with movprfx
 199
 200 movprfx z0.d, p0/z, z7.d
 201 ld1h    { z0.d }, p0/z, [z0.d]
 202 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 203 // CHECK-NEXT: ld1h    { z0.d }, p0/z, [z0.d]
 204 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 205
 206 movprfx z0, z7
 207 ld1h    { z0.d }, p0/z, [z0.d]
 208 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 209 // CHECK-NEXT: ld1h    { z0.d }, p0/z, [z0.d]
 210 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: