test/MC/AArch64/SVE/ld1sb-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid operand (.b)
   5
   6 ld1sb z23.b, p0/z, [x13, #1, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   8 // CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ld1sb z29.b, p0/z, [x3, #1, MUL VL]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  13 // CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16
  17 // --------------------------------------------------------------------------//
  18 // Immediate out of lower bound [-8, 7].
  19
  20 ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
  21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  22 // CHECK-NEXT: ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
  23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  24
  25 ld1sb z10.h, p5/z, [x16, #8, MUL VL]
  26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  27 // CHECK-NEXT: ld1sb z10.h, p5/z, [x16, #8, MUL VL]
  28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  29
  30 ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  32 // CHECK-NEXT: ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 ld1sb z29.s, p5/z, [x15, #8, MUL VL]
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  37 // CHECK-NEXT: ld1sb z29.s, p5/z, [x15, #8, MUL VL]
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40 ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  42 // CHECK-NEXT: ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
  43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  44
  45 ld1sb z27.d, p1/z, [x26, #8, MUL VL]
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  47 // CHECK-NEXT: ld1sb z27.d, p1/z, [x26, #8, MUL VL]
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50
  51 // --------------------------------------------------------------------------//
  52 // restricted predicate has range [0, 7].
  53
  54 ld1sb z9.h, p8/z, [x25, #1, MUL VL]
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  56 // CHECK-NEXT: ld1sb z9.h, p8/z, [x25, #1, MUL VL]
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 ld1sb z12.s, p8/z, [x13, #1, MUL VL]
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  61 // CHECK-NEXT: ld1sb z12.s, p8/z, [x13, #1, MUL VL]
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 ld1sb z4.d, p8/z, [x11, #1, MUL VL]
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  66 // CHECK-NEXT: ld1sb z4.d, p8/z, [x11, #1, MUL VL]
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69
  70 // --------------------------------------------------------------------------//
  71 // Invalid vector list.
  72
  73 ld1sb { }, p0/z, [x1, #1, MUL VL]
  74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  75 // CHECK-NEXT: ld1sb { }, p0/z, [x1, #1, MUL VL]
  76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  77
  78 ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
  79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  80 // CHECK-NEXT: ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
  81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  82
  83 ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
  84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  85 // CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
  86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  87
  88
  89 // --------------------------------------------------------------------------//
  90 // Invalid scalar + scalar addressing modes
  91
  92 ld1sb z0.h, p0/z, [x0, xzr]
  93 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
  94 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr]
  95 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  96
  97 ld1sb z0.h, p0/z, [x0, x0, lsl #1]
  98 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
  99 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1]
 100 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 101
 102 ld1sb z0.h, p0/z, [x0, w0]
 103 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 104 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0]
 105 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 106
 107 ld1sb z0.h, p0/z, [x0, w0, uxtw]
 108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 109 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
 110 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 111
 112 // --------------------------------------------------------------------------//
 113 // Invalid scalar + vector addressing modes
 114
 115 ld1sb z0.d, p0/z, [x0, z0.b]
 116 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 117 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b]
 118 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 119
 120 ld1sb z0.d, p0/z, [x0, z0.h]
 121 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 122 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h]
 123 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 124
 125 ld1sb z0.d, p0/z, [x0, z0.s]
 126 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 127 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s]
 128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 129
 130 ld1sb z0.s, p0/z, [x0, z0.s]
 131 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 132 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s]
 133 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 134
 135 ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1]
 136 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 137 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1]
 138 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 139
 140 ld1sb z0.s, p0/z, [x0, z0.s, lsl #0]
 141 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 142 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, lsl #0]
 143 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 144
 145 ld1sb z0.d, p0/z, [x0, z0.d, lsl #1]
 146 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 147 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, lsl #1]
 148 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 149
 150 ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 151 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 152 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 153 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 154
 155
 156 // --------------------------------------------------------------------------//
 157 // Invalid vector + immediate addressing modes
 158
 159 ld1sb z0.s, p0/z, [z0.s, #-1]
 160 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
 161 // CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #-1]
 162 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 163
 164 ld1sb z0.s, p0/z, [z0.s, #32]
 165 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
 166 // CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #32]
 167 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 168
 169 ld1sb z0.d, p0/z, [z0.d, #-1]
 170 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
 171 // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #-1]
 172 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 173
 174 ld1sb z0.d, p0/z, [z0.d, #32]
 175 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
 176 // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32]
 177 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 178
 179
 180 // --------------------------------------------------------------------------//
 181 // Negative tests for instructions that are incompatible with movprfx
 182
 183 movprfx z0.d, p0/z, z7.d
 184 ld1sb   { z0.d }, p0/z, [z0.d]
 185 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 186 // CHECK-NEXT: ld1sb   { z0.d }, p0/z, [z0.d]
 187 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 188
 189 movprfx z0, z7
 190 ld1sb   { z0.d }, p0/z, [z0.d]
 191 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 192 // CHECK-NEXT: ld1sb   { z0.d }, p0/z, [z0.d]
 193 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: