[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / ld2h-diagnostics.s
blob1c6fb59e29cfea9015be851ee9baa90dae5aa57c
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // --------------------------------------------------------------------------//
5 // Immediate out of lower bound [-16, 14].
7 ld2h {z12.h, z13.h}, p4/z, [x12, #-18, MUL VL]
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
9 // CHECK-NEXT: ld2h {z12.h, z13.h}, p4/z, [x12, #-18, MUL VL]
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 ld2h {z7.h, z8.h}, p3/z, [x1, #16, MUL VL]
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
14 // CHECK-NEXT: ld2h {z7.h, z8.h}, p3/z, [x1, #16, MUL VL]
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 // --------------------------------------------------------------------------//
19 // Immediate not a multiple of two.
21 ld2h {z12.h, z13.h}, p4/z, [x12, #-7, MUL VL]
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
23 // CHECK-NEXT: ld2h {z12.h, z13.h}, p4/z, [x12, #-7, MUL VL]
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL]
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
28 // CHECK-NEXT: ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL]
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32 // --------------------------------------------------------------------------//
33 // Invalid scalar + scalar addressing modes
35 ld2h { z0.h, z1.h }, p0/z, [x0, x0]
36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
37 // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0]
38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40 ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
42 // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45 ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
47 // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50 ld2h { z0.h, z1.h }, p0/z, [x0, w0]
51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
52 // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0]
53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55 ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
57 // CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
61 // --------------------------------------------------------------------------//
62 // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
64 ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
66 // CHECK-NEXT: ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
70 // --------------------------------------------------------------------------//
71 // Invalid vector list.
73 ld2h { }, p0/z, [x0]
74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
75 // CHECK-NEXT: ld2h { }, p0/z, [x0]
76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
78 ld2h { z0.h, z1.h, z2.h }, p0/z, [x0]
79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
80 // CHECK-NEXT: ld2h { z0.h, z1.h, z2.h }, p0/z, [x0]
81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
83 ld2h { z0.h, z1.s }, p0/z, [x0]
84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
85 // CHECK-NEXT: ld2h { z0.h, z1.s }, p0/z, [x0]
86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
88 ld2h { z0.h, z2.h }, p0/z, [x0]
89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
90 // CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0]
91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
93 ld2h { v0.2d, v1.2d }, p0/z, [x0]
94 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
95 // CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0]
96 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
99 // --------------------------------------------------------------------------//
100 // Negative tests for instructions that are incompatible with movprfx
102 movprfx z21.h, p5/z, z28.h
103 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
104 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
105 // CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
106 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
108 movprfx z21, z28
109 ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
110 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
111 // CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
112 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: