test/MC/AArch64/SVE/ldff1d-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid operand (.b, .h, .s)
   5
   6 ldff1d z4.b, p7/z, [x0]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   8 // CHECK-NEXT: ldff1d z4.b, p7/z, [x0]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ldff1d z4.h, p7/z, [x0]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  13 // CHECK-NEXT: ldff1d z4.h, p7/z, [x0]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 ldff1d z4.s, p7/z, [x0]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  18 // CHECK-NEXT: ldff1d z4.s, p7/z, [x0]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // restricted predicate has range [0, 7].
  23
  24 ldff1d z4.d, p8/z, [x0]
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  26 // CHECK-NEXT: ldff1d z4.d, p8/z, [x0]
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 // --------------------------------------------------------------------------//
  30 // Invalid scalar + scalar addressing modes
  31
  32 ldff1d z0.d, p0/z, [x0, sp]
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
  34 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp]
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 ldff1d z0.d, p0/z, [x0, x0, lsl #1]
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
  39 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1]
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 ldff1d z0.d, p0/z, [x0, w0]
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
  44 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0]
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 ldff1d z0.d, p0/z, [x0, w0, uxtw]
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
  49 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw]
  50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  51
  52
  53 // --------------------------------------------------------------------------//
  54 // Invalid scalar + vector addressing modes
  55
  56 ldff1d z0.d, p0/z, [x0, z0.s]
  57 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  58 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.s]
  59 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  60
  61 ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
  62 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
  63 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, uxtw #2]
  64 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  65
  66 ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
  67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
  68 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl #2]
  69 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  70
  71 ldff1d z0.d, p0/z, [x0, z0.d, lsl]
  72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
  73 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl]
  74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  75
  76
  77 // --------------------------------------------------------------------------//
  78 // Invalid vector + immediate addressing modes
  79
  80 ldff1d z0.s, p0/z, [z0.s]
  81 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  82 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s]
  83 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  84
  85 ldff1d z0.s, p0/z, [z0.s, #8]
  86 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  87 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8]
  88 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  89
  90 ldff1d z0.d, p0/z, [z0.d, #-8]
  91 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
  92 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-8]
  93 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  94
  95 ldff1d z0.d, p0/z, [z0.d, #-1]
  96 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
  97 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-1]
  98 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  99
 100 ldff1d z0.d, p0/z, [z0.d, #249]
 101 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 102 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #249]
 103 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 104
 105 ldff1d z0.d, p0/z, [z0.d, #256]
 106 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 107 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #256]
 108 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 109
 110 ldff1d z0.d, p0/z, [z0.d, #3]
 111 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 112 // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3]
 113 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 114
 115
 116 // --------------------------------------------------------------------------//
 117 // Negative tests for instructions that are incompatible with movprfx
 118
 119 movprfx z0.d, p0/z, z7.d
 120 ldff1d  { z0.d }, p0/z, [z0.d]
 121 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 122 // CHECK-NEXT: ldff1d  { z0.d }, p0/z, [z0.d]
 123 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 124
 125 movprfx z0, z7
 126 ldff1d  { z0.d }, p0/z, [z0.d]
 127 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 128 // CHECK-NEXT: ldff1d  { z0.d }, p0/z, [z0.d]
 129 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: