test/MC/AArch64/SVE/ldnf1d-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Immediate out of lower bound [-8, 7].
   5
   6 ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
   8 // CHECK-NEXT: ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  13 // CHECK-NEXT: ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16
  17 // --------------------------------------------------------------------------//
  18 // restricted predicate has range [0, 7].
  19
  20 ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
  21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  22 // CHECK-NEXT: ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
  23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  24
  25
  26 // --------------------------------------------------------------------------//
  27 // Invalid vector list.
  28
  29 ldnf1d { }, p0/z, [x1, #1, MUL VL]
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  31 // CHECK-NEXT: ldnf1d { }, p0/z, [x1, #1, MUL VL]
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
  35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  36 // CHECK-NEXT: ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
  37 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  38
  39 ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
  40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  41 // CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
  42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  43
  44
  45 // --------------------------------------------------------------------------//
  46 // Negative tests for instructions that are incompatible with movprfx
  47
  48 movprfx z21.d, p5/z, z28.d
  49 ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  51 // CHECK-NEXT: ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 movprfx z21, z28
  55 ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  57 // CHECK-NEXT: ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: