test/MC/AArch64/SVE/ldnf1w-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Immediate out of lower bound [-8, 7].
   5
   6 ldnf1w z30.s, p6/z, [x25, #-9, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
   8 // CHECK-NEXT: ldnf1w z30.s, p6/z, [x25, #-9, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ldnf1w z29.s, p5/z, [x15, #8, MUL VL]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  13 // CHECK-NEXT: ldnf1w z29.s, p5/z, [x15, #8, MUL VL]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 ldnf1w z28.d, p2/z, [x28, #-9, MUL VL]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  18 // CHECK-NEXT: ldnf1w z28.d, p2/z, [x28, #-9, MUL VL]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  23 // CHECK-NEXT: ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26
  27 // --------------------------------------------------------------------------//
  28 // restricted predicate has range [0, 7].
  29
  30 ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  32 // CHECK-NEXT: ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  37 // CHECK-NEXT: ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40
  41 // --------------------------------------------------------------------------//
  42 // Invalid vector list.
  43
  44 ldnf1w { }, p0/z, [x1, #1, MUL VL]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  46 // CHECK-NEXT: ldnf1w { }, p0/z, [x1, #1, MUL VL]
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  51 // CHECK-NEXT: ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  56 // CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59
  60 // --------------------------------------------------------------------------//
  61 // Negative tests for instructions that are incompatible with movprfx
  62
  63 movprfx z21.d, p5/z, z28.d
  64 ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  66 // CHECK-NEXT: ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69 movprfx z21, z28
  70 ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  72 // CHECK-NEXT: ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: