[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / pfirst-diagnostics.s
blob4d88274968f99b79bf476acc07002e08d5e33b38
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid predicate
7 pfirst p0.h, p15, p0.h
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
9 // CHECK-NEXT: pfirst p0.h, p15, p0.h
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 pfirst p0.b, p15/z, p0.b
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14 // CHECK-NEXT: pfirst p0.b, p15/z, p0.b
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 pfirst p0.b, p15/m, p0.b
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
19 // CHECK-NEXT: pfirst p0.b, p15/m, p0.b
20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22 pfirst p0.b, p15.b, p0.b
23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
24 // CHECK-NEXT: pfirst p0.b, p15.b, p0.b
25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
27 pfirst p0.b, p15.q, p0.b
28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
29 // CHECK-NEXT: pfirst p0.b, p15.q, p0.b
30 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33 // ------------------------------------------------------------------------- //
34 // Tied operands must match
36 pfirst p0.b, p15, p1.b
37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
38 // CHECK-NEXT: pfirst p0.b, p15, p1.b
39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: