[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / pnext-diagnostics.s
blob6e1b2317f501f7c514a808ecacfe5c2d4fa13216
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Unexpected type suffix
7 pnext p0.b, p15.b, p0.b
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
9 // CHECK-NEXT: pnext p0.b, p15.b, p0.b
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 pnext p0.b, p15.q, p0.b
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
14 // CHECK-NEXT: pnext p0.b, p15.q, p0.b
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 // ------------------------------------------------------------------------- //
19 // Tied operands must match
21 pnext p0.b, p15, p1.b
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
23 // CHECK-NEXT: pnext p0.b, p15, p1.b
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: