test/MC/AArch64/SVE/prfh-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3
   4 // --------------------------------------------------------------------------//
   5 // invalid/missing predicate operation specifier
   6
   7 prfh p0, [x0]
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
   9 // CHECK-NEXT: prfh p0, [x0]
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12 prfh #16, p0, [x0]
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch operand out of range, [0,15] expected
  14 // CHECK-NEXT: prfh #16, p0, [x0]
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 prfh plil1keep, p0, [x0]
  18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
  19 // CHECK-NEXT: prfh plil1keep, p0, [x0]
  20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  21
  22 prfh #pldl1keep, p0, [x0]
  23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate value expected for prefetch operand
  24 // CHECK-NEXT: prfh #pldl1keep, p0, [x0]
  25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  26
  27
  28 // --------------------------------------------------------------------------//
  29 // invalid scalar + scalar addressing modes
  30
  31 prfh #0, p0, [x0, #-33, mul vl]
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
  33 // CHECK-NEXT: prfh #0, p0, [x0, #-33, mul vl]
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 prfh #0, p0, [x0, #32, mul vl]
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
  38 // CHECK-NEXT: prfh #0, p0, [x0, #32, mul vl]
  39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  40
  41 prfh #0, p0, [x0, w0]
  42 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  43 // CHECK-NEXT: prfh #0, p0, [x0, w0]
  44 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  45
  46 prfh #0, p0, [x0, x0, uxtw]
  47 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  48 // CHECK-NEXT: prfh #0, p0, [x0, x0, uxtw]
  49 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  50
  51 prfh #0, p0, [x0, x0, lsl #2]
  52 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
  53 // CHECK-NEXT: prfh #0, p0, [x0, x0, lsl #2]
  54 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  55
  56
  57 // --------------------------------------------------------------------------//
  58 // Invalid scalar + vector addressing modes
  59
  60 prfh #0, p0, [x0, z0.h]
  61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  62 // CHECK-NEXT: prfh #0, p0, [x0, z0.h]
  63 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  64
  65 prfh #0, p0, [x0, z0.s]
  66 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
  67 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
  68 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  69
  70 prfh #0, p0, [x0, z0.s]
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
  72 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  74
  75 prfh #0, p0, [x0, z0.s, uxtw #2]
  76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
  77 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2]
  78 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  79
  80 prfh #0, p0, [x0, z0.s, lsl #1]
  81 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
  82 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1]
  83 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  84
  85 prfh #0, p0, [x0, z0.d, lsl #2]
  86 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
  87 // CHECK-NEXT: prfh #0, p0, [x0, z0.d, lsl #2]
  88 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  89
  90 prfh #0, p0, [x0, z0.d, sxtw #2]
  91 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
  92 // CHECK-NEXT: prfh #0, p0, [x0, z0.d, sxtw #2]
  93 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  94
  95
  96 // --------------------------------------------------------------------------//
  97 // Invalid vector + immediate addressing modes
  98
  99 prfh #0, p0, [z0.s, #-2]
 100 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 101 // CHECK-NEXT: prfh #0, p0, [z0.s, #-2]
 102 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 103
 104 prfh #0, p0, [z0.s, #-1]
 105 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 106 // CHECK-NEXT: prfh #0, p0, [z0.s, #-1]
 107 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 108
 109 prfh #0, p0, [z0.s, #63]
 110 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 111 // CHECK-NEXT: prfh #0, p0, [z0.s, #63]
 112 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 113
 114 prfh #0, p0, [z0.s, #64]
 115 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 116 // CHECK-NEXT: prfh #0, p0, [z0.s, #64]
 117 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 118
 119 prfh #0, p0, [z0.s, #3]
 120 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 121 // CHECK-NEXT: prfh #0, p0, [z0.s, #3]
 122 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 123
 124 prfh #0, p0, [z0.d, #-2]
 125 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 126 // CHECK-NEXT: prfh #0, p0, [z0.d, #-2]
 127 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 128
 129 prfh #0, p0, [z0.d, #-1]
 130 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 131 // CHECK-NEXT: prfh #0, p0, [z0.d, #-1]
 132 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 133
 134 prfh #0, p0, [z0.d, #63]
 135 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 136 // CHECK-NEXT: prfh #0, p0, [z0.d, #63]
 137 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 138
 139 prfh #0, p0, [z0.d, #64]
 140 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 141 // CHECK-NEXT: prfh #0, p0, [z0.d, #64]
 142 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 143
 144 prfh #0, p0, [z0.d, #3]
 145 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
 146 // CHECK-NEXT: prfh #0, p0, [z0.d, #3]
 147 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 148
 149 // --------------------------------------------------------------------------//
 150 // Invalid predicate
 151
 152 prfh #0, p8, [x0]
 153 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
 154 // CHECK-NEXT: prfh #0, p8, [x0]
 155 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 156
 157 prfh #0, p7.b, [x0]
 158 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
 159 // CHECK-NEXT: prfh #0, p7.b, [x0]
 160 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 161
 162 prfh #0, p7.q, [x0]
 163 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
 164 // CHECK-NEXT: prfh #0, p7.q, [x0]
 165 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 166
 167
 168 // --------------------------------------------------------------------------//
 169 // Negative tests for instructions that are incompatible with movprfx
 170
 171 movprfx z0.d, p0/z, z7.d
 172 prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 173 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 174 // CHECK-NEXT: prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 175 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 176
 177 movprfx z0, z7
 178 prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 179 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 180 // CHECK-NEXT: prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 181 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: