test/MC/AArch64/SVE/sdot-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3
   4 // ------------------------------------------------------------------------- //
   5 // Invalid element size
   6
   7 sdot  z0.s, z1.h, z31.h
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   9 // CHECK-NEXT: sdot  z0.s, z1.h, z31.h
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12 sdot  z0.d, z1.b, z31.b
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  14 // CHECK-NEXT: sdot  z0.d, z1.b, z31.b
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 sdot  z0.d, z1.s, z31.s
  18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  19 // CHECK-NEXT: sdot  z0.d, z1.s, z31.s
  20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  21
  22
  23 // ------------------------------------------------------------------------- //
  24 // Invalid restricted register for indexed vector.
  25
  26 sdot  z0.s, z1.b, z8.b[3]
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  28 // CHECK-NEXT: sdot  z0.s, z1.b, z8.b[3]
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 sdot  z0.d, z1.h, z16.h[1]
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  33 // CHECK-NEXT: sdot  z0.d, z1.h, z16.h[1]
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36
  37 // ------------------------------------------------------------------------- //
  38 // Invalid element index
  39
  40 sdot  z0.s, z1.b, z7.b[-1]
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  42 // CHECK-NEXT: sdot  z0.s, z1.b, z7.b[-1]
  43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  44
  45 sdot  z0.s, z1.b, z7.b[4]
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  47 // CHECK-NEXT: sdot  z0.s, z1.b, z7.b[4]
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 sdot  z0.d, z1.h, z15.h[-1]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
  52 // CHECK-NEXT: sdot  z0.d, z1.h, z15.h[-1]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 sdot  z0.d, z1.h, z15.h[2]
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
  57 // CHECK-NEXT: sdot  z0.d, z1.h, z15.h[2]
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60
  61 // --------------------------------------------------------------------------//
  62 // Negative tests for instructions that are incompatible with movprfx
  63
  64 movprfx z0.d, p0/z, z7.d
  65 sdot  z0.d, z1.h, z31.h
  66 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  67 // CHECK-NEXT: sdot  z0.d, z1.h, z31.h
  68 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  69
  70 movprfx z0.d, p0/z, z7.d
  71 sdot  z0.d, z1.h, z15.h[1]
  72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  73 // CHECK-NEXT: sdot  z0.d, z1.h, z15.h[1]
  74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: