test/MC/AArch64/SVE/sqdecp-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // Invalid result register
   5
   6 sqdecp sp, p0
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
   8 // CHECK-NEXT: sqdecp sp, p0
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 sqdecp z0.b, p0
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  13 // CHECK-NEXT: sqdecp z0.b, p0
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 sqdecp w0, p0.b
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  18 // CHECK-NEXT: sqdecp w0, p0.b
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 sqdecp x0, p0.b, x1
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  23 // CHECK-NEXT: sqdecp x0, p0.b, x1
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 sqdecp x0, p0.b, w1
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
  28 // CHECK-NEXT: sqdecp x0, p0.b, w1
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31
  32 // ------------------------------------------------------------------------- //
  33 // Invalid predicate operand
  34
  35 sqdecp x0, p0
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  37 // CHECK-NEXT: sqdecp x0, p0
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40 sqdecp x0, p0/z
  41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  42 // CHECK-NEXT: sqdecp x0, p0/z
  43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  44
  45 sqdecp x0, p0/m
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  47 // CHECK-NEXT: sqdecp x0, p0/m
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 sqdecp x0, p0.q
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  52 // CHECK-NEXT: sqdecp x0, p0.q
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 sqdecp z0.d, p0.b
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  57 // CHECK-NEXT: sqdecp z0.d, p0.b
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60 sqdecp z0.d, p0.q
  61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  62 // CHECK-NEXT: sqdecp z0.d, p0.q
  63 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  64
  65
  66 // --------------------------------------------------------------------------//
  67 // Negative tests for instructions that are incompatible with movprfx
  68
  69 movprfx z0.d, p0/z, z7.d
  70 sqdecp  z0.d, p0
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  72 // CHECK-NEXT: sqdecp  z0.d, p0
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: