test/MC/AArch64/SVE/st1d-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Immediate out of lower bound [-8, 7].
   5
   6 st1d z25.d, p4, [x16, #-9, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
   8 // CHECK-NEXT: st1d z25.d, p4, [x16, #-9, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 // Immediate out of upper bound [-8, 7].
  12 st1d z16.d, p4, [x2, #8, MUL VL]
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  14 // CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL]
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 // --------------------------------------------------------------------------//
  18 // Invalid predicate
  19
  20 st1d z12.d, p8, [x4, #14, MUL VL]
  21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  22 // CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL]
  23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  24
  25 st1d z12.d, p7.b, [x4, #14, MUL VL]
  26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  27 // CHECK-NEXT: st1d z12.d, p7.b, [x4, #14, MUL VL]
  28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  29
  30 st1d z12.d, p7.q, [x4, #14, MUL VL]
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  32 // CHECK-NEXT: st1d z12.d, p7.q, [x4, #14, MUL VL]
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 // --------------------------------------------------------------------------//
  36 // Invalid vector list
  37
  38 st1d { }, p0, [x0]
  39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  40 // CHECK-NEXT: st1d { }, p0, [x0]
  41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  42
  43 st1d { z1.d, z2.d }, p0, [x0]
  44 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  45 // CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0]
  46 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  47
  48 st1d { v0.2d }, p0, [x0]
  49 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  50 // CHECK-NEXT: st1d { v0.2d }, p0, [x0]
  51 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  52
  53
  54 // --------------------------------------------------------------------------//
  55 // Invalid scalar + scalar addressing modes
  56
  57 st1d z0.d, p0, [x0, x0]
  58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  59 // CHECK-NEXT: st1d z0.d, p0, [x0, x0]
  60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  61
  62 st1d z0.d, p0, [x0, xzr]
  63 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  64 // CHECK-NEXT: st1d z0.d, p0, [x0, xzr]
  65 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  66
  67 st1d z0.d, p0, [x0, x0, lsl #2]
  68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  69 // CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2]
  70 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  71
  72 st1d z0.d, p0, [x0, w0]
  73 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  74 // CHECK-NEXT: st1d z0.d, p0, [x0, w0]
  75 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  76
  77 st1d z0.d, p0, [x0, w0, uxtw]
  78 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
  79 // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw]
  80 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  81
  82
  83 // --------------------------------------------------------------------------//
  84 // Invalid scalar + vector addressing modes
  85
  86 st1d z0.d, p0, [x0, z0.s]
  87 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  88 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s]
  89 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  90
  91 st1d z0.d, p0, [x0, z0.d, uxtw #2]
  92 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
  93 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2]
  94 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  95
  96 st1d z0.d, p0, [x0, z0.d, lsl #2]
  97 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
  98 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2]
  99 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 100
 101 st1d z0.d, p0, [x0, z0.d, lsl]
 102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 103 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl]
 104 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 105
 106
 107 // --------------------------------------------------------------------------//
 108 // Invalid vector + immediate addressing modes
 109
 110 st1d z0.s, p0, [z0.s]
 111 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 112 // CHECK-NEXT: st1d z0.s, p0, [z0.s]
 113 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 114
 115 st1d z0.s, p0, [z0.s, #8]
 116 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 117 // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8]
 118 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 119
 120 st1d z0.d, p0, [z0.d, #-1]
 121 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 122 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1]
 123 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 124
 125 st1d z0.d, p0, [z0.d, #-8]
 126 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 127 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8]
 128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 129
 130 st1d z0.d, p0, [z0.d, #249]
 131 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 132 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #249]
 133 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 134
 135 st1d z0.d, p0, [z0.d, #256]
 136 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 137 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #256]
 138 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 139
 140 st1d z0.d, p0, [z0.d, #3]
 141 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
 142 // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3]
 143 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 144
 145
 146 // --------------------------------------------------------------------------//
 147 // Negative tests for instructions that are incompatible with movprfx
 148
 149 movprfx z31.d, p7/z, z6.d
 150 st1d    { z31.d }, p7, [z31.d, #248]
 151 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 152 // CHECK-NEXT: st1d    { z31.d }, p7, [z31.d, #248]
 153 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 154
 155 movprfx z31, z6
 156 st1d    { z31.d }, p7, [z31.d, #248]
 157 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 158 // CHECK-NEXT: st1d    { z31.d }, p7, [z31.d, #248]
 159 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: