[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / st3w-diagnostics.s
blob12b92ac8fa067922e3989031b7e5e6d2f129916c
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // --------------------------------------------------------------------------//
5 // Immediate out of lower bound [-24, 21].
7 st3w {z12.s, z13.s, z14.s}, p4, [x12, #-27, MUL VL]
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
9 // CHECK-NEXT: st3w {z12.s, z13.s, z14.s}, p4, [x12, #-27, MUL VL]
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 st3w {z7.s, z8.s, z9.s}, p3, [x1, #24, MUL VL]
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
14 // CHECK-NEXT: st3w {z7.s, z8.s, z9.s}, p3, [x1, #24, MUL VL]
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 // --------------------------------------------------------------------------//
19 // Immediate not a multiple of three.
21 st3w {z12.s, z13.s, z14.s}, p4, [x12, #-7, MUL VL]
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
23 // CHECK-NEXT: st3w {z12.s, z13.s, z14.s}, p4, [x12, #-7, MUL VL]
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL]
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
28 // CHECK-NEXT: st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL]
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32 // --------------------------------------------------------------------------//
33 // Invalid scalar + scalar addressing modes
35 st3w { z0.s, z1.s, z2.s }, p0, [x0, x0]
36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
37 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0]
38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40 st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr]
41 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
42 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr]
43 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45 st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3]
46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
47 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3]
48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50 st3w { z0.s, z1.s, z2.s }, p0, [x0, w0]
51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
52 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0]
53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55 st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
57 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
61 // --------------------------------------------------------------------------//
62 // Invalid predicate
64 st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
66 // CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
69 st3w {z2.s, z3.s, z4.s}, p7.b, [x15, #10, MUL VL]
70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
71 // CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p7.b, [x15, #10, MUL VL]
72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
74 st3w {z2.s, z3.s, z4.s}, p7.q, [x15, #10, MUL VL]
75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
76 // CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p7.q, [x15, #10, MUL VL]
77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
80 // --------------------------------------------------------------------------//
81 // Invalid vector list.
83 st3w { }, p0, [x0]
84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
85 // CHECK-NEXT: st3w { }, p0, [x0]
86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
88 st3w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
90 // CHECK-NEXT: st3w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
93 st3w { z0.s, z1.s, z2.d }, p0, [x0]
94 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
95 // CHECK-NEXT: st3w { z0.s, z1.s, z2.d }, p0, [x0]
96 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
98 st3w { z0.s, z1.s, z3.s }, p0, [x0]
99 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
100 // CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0]
101 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
103 st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
104 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
105 // CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
106 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
109 // --------------------------------------------------------------------------//
110 // Negative tests for instructions that are incompatible with movprfx
112 movprfx z21.s, p5/z, z28.s
113 st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
114 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
115 // CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
116 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
118 movprfx z21, z28
119 st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
120 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
121 // CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
122 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: