[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / AArch64 / SVE / uqincw-diagnostics.s
blob0ad3624230b7d945cddc70c544e27396d0e23f9f
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // ------------------------------------------------------------------------- //
4 // Invalid result register
6 uqincw wsp
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
8 // CHECK-NEXT: uqincw wsp
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 uqincw sp
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
13 // CHECK-NEXT: uqincw sp
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 uqincw z0.d
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18 // CHECK-NEXT: uqincw z0.d
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22 // ------------------------------------------------------------------------- //
23 // Operands not matching up (unsigned inc only has one register operand)
25 uqincw x0, w0
26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
27 // CHECK-NEXT: uqincw x0, w0
28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30 uqincw w0, w0
31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
32 // CHECK-NEXT: uqincw w0, w0
33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35 uqincw x0, x0
36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
37 // CHECK-NEXT: uqincw x0, x0
38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
41 // ------------------------------------------------------------------------- //
42 // Immediate not compatible with encode/decode function.
44 uqincw x0, all, mul #-1
45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
46 // CHECK-NEXT: uqincw x0, all, mul #-1
47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
49 uqincw x0, all, mul #0
50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
51 // CHECK-NEXT: uqincw x0, all, mul #0
52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
54 uqincw x0, all, mul #17
55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
56 // CHECK-NEXT: uqincw x0, all, mul #17
57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
60 // ------------------------------------------------------------------------- //
61 // Invalid predicate patterns
63 uqincw x0, vl512
64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
65 // CHECK-NEXT: uqincw x0, vl512
66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
68 uqincw x0, vl9
69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
70 // CHECK-NEXT: uqincw x0, vl9
71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
73 uqincw x0, #-1
74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
75 // CHECK-NEXT: uqincw x0, #-1
76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
78 uqincw x0, #32
79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
80 // CHECK-NEXT: uqincw x0, #32
81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
84 // --------------------------------------------------------------------------//
85 // Negative tests for instructions that are incompatible with movprfx
87 movprfx z0.s, p0/z, z7.s
88 uqincw z0.s
89 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
90 // CHECK-NEXT: uqincw z0.s
91 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
93 movprfx z0.s, p0/z, z7.s
94 uqincw z0.s, pow2, mul #16
95 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
96 // CHECK-NEXT: uqincw z0.s, pow2, mul #16
97 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
99 movprfx z0.s, p0/z, z7.s
100 uqincw z0.s, pow2
101 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
102 // CHECK-NEXT: uqincw z0.s, pow2
103 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: