[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / MC / RISCV / rv64d-invalid.s
blob0f508aafd9be5d1ca62aa5c14253f05833b609ac
1 # RUN: not llvm-mc -triple riscv64 -mattr=+d < %s 2>&1 | FileCheck %s
3 # Integer registers where FP regs are expected
4 fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
5 fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
6 fmv.x.d ft2, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
8 # FP registers where integer regs are expected
9 fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
10 fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
11 fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction