| blob | 97871d18f918f264ef8988870529f2226791f853 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -instcombine -S | FileCheck %s
4 define <4 x i32> @lshr_non_splat_vector(<4 x i32> %A) {
5 ; CHECK-LABEL: @lshr_non_splat_vector(
6 ; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3>
7 ; CHECK-NEXT: ret <4 x i32> [[B]]
8 ;
9 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3>
10 ret <4 x i32> %B
11 }
13 define <4 x i32> @shl_non_splat_vector(<4 x i32> %A) {
14 ; CHECK-LABEL: @shl_non_splat_vector(
15 ; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3>
16 ; CHECK-NEXT: ret <4 x i32> [[B]]
17 ;
18 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3>
19 ret <4 x i32> %B
20 }
22 define i32 @test6(i32 %A) {
23 ; CHECK-LABEL: @test6(
24 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6
25 ; CHECK-NEXT: ret i32 [[C]]
26 ;
27 %B = shl i32 %A, 1 ;; convert to an mul instruction
28 %C = mul i32 %B, 3
29 ret i32 %C
30 }
32 define i32 @test6a(i32 %A) {
33 ; CHECK-LABEL: @test6a(
34 ; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6
35 ; CHECK-NEXT: ret i32 [[C]]
36 ;
37 %B = mul i32 %A, 3
38 %C = shl i32 %B, 1 ;; convert to an mul instruction
39 ret i32 %C
40 }
42 ;; (A << 5) << 3 === A << 8 == 0
43 define i8 @test8(i8 %A) {
44 ; CHECK-LABEL: @test8(
45 ; CHECK-NEXT: ret i8 0
46 ;
47 %B = shl i8 %A, 5
48 %C = shl i8 %B, 3
49 ret i8 %C
50 }
52 ;; (A << 7) >> 7 === A & 1
53 define i8 @test9(i8 %A) {
54 ; CHECK-LABEL: @test9(
55 ; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 1
56 ; CHECK-NEXT: ret i8 [[B]]
57 ;
58 %B = shl i8 %A, 7
59 %C = lshr i8 %B, 7
60 ret i8 %C
61 }
63 ;; (A >> 7) << 7 === A & 128
65 define i8 @test10(i8 %A) {
66 ; CHECK-LABEL: @test10(
67 ; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -128
68 ; CHECK-NEXT: ret i8 [[B]]
69 ;
70 %B = lshr i8 %A, 7
71 %C = shl i8 %B, 7
72 ret i8 %C
73 }
75 ;; Allow the simplification when the lshr shift is exact.
76 define i8 @test10a(i8 %A) {
77 ; CHECK-LABEL: @test10a(
78 ; CHECK-NEXT: ret i8 [[A:%.*]]
79 ;
80 %B = lshr exact i8 %A, 7
81 %C = shl i8 %B, 7
82 ret i8 %C
83 }
85 ;; This transformation is deferred to DAGCombine:
86 ;; (A >> 3) << 4 === (A & 0x1F) << 1
87 ;; The shl may be valuable to scalar evolution.
88 define i8 @test11(i8 %x) {
89 ; CHECK-LABEL: @test11(
90 ; CHECK-NEXT: [[A:%.*]] = mul i8 [[X:%.*]], 3
91 ; CHECK-NEXT: [[B:%.*]] = lshr i8 [[A]], 3
92 ; CHECK-NEXT: [[C:%.*]] = shl i8 [[B]], 4
93 ; CHECK-NEXT: ret i8 [[C]]
94 ;
95 %a = mul i8 %x, 3
96 %B = lshr i8 %a, 3
97 %C = shl i8 %B, 4
98 ret i8 %C
99 }
101 ;; Allow the simplification in InstCombine when the lshr shift is exact.
102 define i8 @test11a(i8 %A) {
103 ; CHECK-LABEL: @test11a(
104 ; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6
105 ; CHECK-NEXT: ret i8 [[C]]
106 ;
107 %a = mul i8 %A, 3
108 %B = lshr exact i8 %a, 3
109 %C = shl i8 %B, 4
110 ret i8 %C
111 }
113 ;; This is deferred to DAGCombine unless %B is single-use.
114 ;; (A >> 8) << 8 === A & -256
115 define i32 @test12(i32 %A) {
116 ; CHECK-LABEL: @test12(
117 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -256
118 ; CHECK-NEXT: ret i32 [[TMP1]]
119 ;
120 %B = ashr i32 %A, 8
121 %C = shl i32 %B, 8
122 ret i32 %C
123 }
125 ;; ((A >>s 6) << 6 === (A & FFFFFFC0)
126 define i8 @shishi(i8 %x) {
127 ; CHECK-LABEL: @shishi(
128 ; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 6
129 ; CHECK-NEXT: [[B:%.*]] = and i8 [[X]], -64
130 ; CHECK-NEXT: [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5
131 ; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]]
132 ; CHECK-NEXT: ret i8 [[R]]
133 ;
134 %a = ashr i8 %x, 6
135 %b = shl i8 %a, 6
136 %extra_use_of_a = mul i8 %a, 5
137 %r = sdiv i8 %extra_use_of_a, %b
138 ret i8 %r
139 }
141 ;; This transformation is deferred to DAGCombine:
142 ;; (A >> 3) << 4 === (A & -8) * 2
143 ;; The shl may be valuable to scalar evolution.
144 define i8 @test13(i8 %x) {
145 ; CHECK-LABEL: @test13(
146 ; CHECK-NEXT: [[A:%.*]] = mul i8 [[X:%.*]], 3
147 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[A]], 3
148 ; CHECK-NEXT: [[C:%.*]] = shl i8 [[TMP1]], 4
149 ; CHECK-NEXT: ret i8 [[C]]
150 ;
151 %a = mul i8 %x, 3
152 %B = ashr i8 %a, 3
153 %C = shl i8 %B, 4
154 ret i8 %C
155 }
157 define i8 @test13a(i8 %A) {
158 ; CHECK-LABEL: @test13a(
159 ; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6
160 ; CHECK-NEXT: ret i8 [[C]]
161 ;
162 %a = mul i8 %A, 3
163 %B = ashr exact i8 %a, 3
164 %C = shl i8 %B, 4
165 ret i8 %C
166 }
168 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
169 define i32 @test14(i32 %A) {
170 ; CHECK-LABEL: @test14(
171 ; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -19760
172 ; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744
173 ; CHECK-NEXT: ret i32 [[C]]
174 ;
175 %B = lshr i32 %A, 4
176 %C = or i32 %B, 1234
177 %D = shl i32 %C, 4
178 ret i32 %D
179 }
181 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
182 define i32 @test14a(i32 %A) {
183 ; CHECK-LABEL: @test14a(
184 ; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], 77
185 ; CHECK-NEXT: ret i32 [[C]]
186 ;
187 %B = shl i32 %A, 4
188 %C = and i32 %B, 1234
189 %D = lshr i32 %C, 4
190 ret i32 %D
191 }
193 define i32 @test15(i1 %C) {
194 ; CHECK-LABEL: @test15(
195 ; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], i32 12, i32 4
196 ; CHECK-NEXT: ret i32 [[A]]
197 ;
198 %A = select i1 %C, i32 3, i32 1
199 %V = shl i32 %A, 2
200 ret i32 %V
201 }
203 define i32 @test15a(i1 %C) {
204 ; CHECK-LABEL: @test15a(
205 ; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 512, i32 128
206 ; CHECK-NEXT: ret i32 [[V]]
207 ;
208 %A = select i1 %C, i8 3, i8 1
209 %shift.upgrd.4 = zext i8 %A to i32
210 %V = shl i32 64, %shift.upgrd.4
211 ret i32 %V
212 }
214 define i1 @test16(i32 %X) {
215 ; CHECK-LABEL: @test16(
216 ; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X:%.*]], 16
217 ; CHECK-NEXT: [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0
218 ; CHECK-NEXT: ret i1 [[TMP_7]]
219 ;
220 %tmp.3 = ashr i32 %X, 4
221 %tmp.6 = and i32 %tmp.3, 1
222 %tmp.7 = icmp ne i32 %tmp.6, 0
223 ret i1 %tmp.7
224 }
226 define i1 @test17(i32 %A) {
227 ; CHECK-LABEL: @test17(
228 ; CHECK-NEXT: [[B_MASK:%.*]] = and i32 [[A:%.*]], -8
229 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872
230 ; CHECK-NEXT: ret i1 [[C]]
231 ;
232 %B = lshr i32 %A, 3
233 %C = icmp eq i32 %B, 1234
234 ret i1 %C
235 }
237 define <2 x i1> @test17vec(<2 x i32> %A) {
238 ; CHECK-LABEL: @test17vec(
239 ; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 -8, i32 -8>
240 ; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872>
241 ; CHECK-NEXT: ret <2 x i1> [[C]]
242 ;
243 %B = lshr <2 x i32> %A, <i32 3, i32 3>
244 %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234>
245 ret <2 x i1> %C
246 }
248 define i1 @test18(i8 %A) {
249 ; CHECK-LABEL: @test18(
250 ; CHECK-NEXT: ret i1 false
251 ;
252 %B = lshr i8 %A, 7
253 ;; false
254 %C = icmp eq i8 %B, 123
255 ret i1 %C
256 }
258 define i1 @test19(i32 %A) {
259 ; CHECK-LABEL: @test19(
260 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 4
261 ; CHECK-NEXT: ret i1 [[C]]
262 ;
263 %B = ashr i32 %A, 2
264 ;; (X & -4) == 0
265 %C = icmp eq i32 %B, 0
266 ret i1 %C
267 }
269 define <2 x i1> @test19vec(<2 x i32> %A) {
270 ; CHECK-LABEL: @test19vec(
271 ; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> [[A:%.*]], <i32 4, i32 4>
272 ; CHECK-NEXT: ret <2 x i1> [[C]]
273 ;
274 %B = ashr <2 x i32> %A, <i32 2, i32 2>
275 %C = icmp eq <2 x i32> %B, zeroinitializer
276 ret <2 x i1> %C
277 }
279 ;; X >u ~4
280 define i1 @test19a(i32 %A) {
281 ; CHECK-LABEL: @test19a(
282 ; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A:%.*]], -5
283 ; CHECK-NEXT: ret i1 [[C]]
284 ;
285 %B = ashr i32 %A, 2
286 %C = icmp eq i32 %B, -1
287 ret i1 %C
288 }
290 define <2 x i1> @test19a_vec(<2 x i32> %A) {
291 ; CHECK-LABEL: @test19a_vec(
292 ; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A:%.*]], <i32 -5, i32 -5>
293 ; CHECK-NEXT: ret <2 x i1> [[C]]
294 ;
295 %B = ashr <2 x i32> %A, <i32 2, i32 2>
296 %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1>
297 ret <2 x i1> %C
298 }
300 define i1 @test20(i8 %A) {
301 ; CHECK-LABEL: @test20(
302 ; CHECK-NEXT: ret i1 false
303 ;
304 %B = ashr i8 %A, 7
305 ;; false
306 %C = icmp eq i8 %B, 123
307 ret i1 %C
308 }
310 define i1 @test21(i8 %A) {
311 ; CHECK-LABEL: @test21(
312 ; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15
313 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8
314 ; CHECK-NEXT: ret i1 [[C]]
315 ;
316 %B = shl i8 %A, 4
317 %C = icmp eq i8 %B, -128
318 ret i1 %C
319 }
321 define i1 @test22(i8 %A) {
322 ; CHECK-LABEL: @test22(
323 ; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15
324 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0
325 ; CHECK-NEXT: ret i1 [[C]]
326 ;
327 %B = shl i8 %A, 4
328 %C = icmp eq i8 %B, 0
329 ret i1 %C
330 }
332 define i8 @test23(i32 %A) {
333 ; CHECK-LABEL: @test23(
334 ; CHECK-NEXT: [[D:%.*]] = trunc i32 [[A:%.*]] to i8
335 ; CHECK-NEXT: ret i8 [[D]]
336 ;
337 ;; casts not needed
338 %B = shl i32 %A, 24
339 %C = ashr i32 %B, 24
340 %D = trunc i32 %C to i8
341 ret i8 %D
342 }
344 define i8 @test24(i8 %X) {
345 ; CHECK-LABEL: @test24(
346 ; CHECK-NEXT: [[Z:%.*]] = and i8 [[X:%.*]], 3
347 ; CHECK-NEXT: ret i8 [[Z]]
348 ;
349 %Y = and i8 %X, -5
350 %Z = shl i8 %Y, 5
351 %Q = ashr i8 %Z, 5
352 ret i8 %Q
353 }
355 define i32 @test25(i32 %tmp.2, i32 %AA) {
356 ; CHECK-LABEL: @test25(
357 ; CHECK-NEXT: [[TMP_3:%.*]] = and i32 [[TMP_2:%.*]], -131072
358 ; CHECK-NEXT: [[X2:%.*]] = add i32 [[TMP_3]], [[AA:%.*]]
359 ; CHECK-NEXT: [[TMP_6:%.*]] = and i32 [[X2]], -131072
360 ; CHECK-NEXT: ret i32 [[TMP_6]]
361 ;
362 %x = lshr i32 %AA, 17
363 %tmp.3 = lshr i32 %tmp.2, 17
364 %tmp.5 = add i32 %tmp.3, %x
365 %tmp.6 = shl i32 %tmp.5, 17
366 ret i32 %tmp.6
367 }
369 define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
370 ; CHECK-LABEL: @test25_vector(
371 ; CHECK-NEXT: [[TMP_3:%.*]] = and <2 x i32> [[TMP_2:%.*]], <i32 -131072, i32 -131072>
372 ; CHECK-NEXT: [[X2:%.*]] = add <2 x i32> [[TMP_3]], [[AA:%.*]]
373 ; CHECK-NEXT: [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072>
374 ; CHECK-NEXT: ret <2 x i32> [[TMP_6]]
375 ;
376 %x = lshr <2 x i32> %AA, <i32 17, i32 17>
377 %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17>
378 %tmp.5 = add <2 x i32> %tmp.3, %x
379 %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17>
380 ret <2 x i32> %tmp.6
381 }
383 ;; handle casts between shifts.
384 define i32 @test26(i32 %A) {
385 ; CHECK-LABEL: @test26(
386 ; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -2
387 ; CHECK-NEXT: ret i32 [[B]]
388 ;
389 %B = lshr i32 %A, 1
390 %C = bitcast i32 %B to i32
391 %D = shl i32 %C, 1
392 ret i32 %D
393 }
396 define i1 @test27(i32 %x) nounwind {
397 ; CHECK-LABEL: @test27(
398 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 8
399 ; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0
400 ; CHECK-NEXT: ret i1 [[Z]]
401 ;
402 %y = lshr i32 %x, 3
403 %z = trunc i32 %y to i1
404 ret i1 %z
405 }
407 define i1 @test28(i8 %x) {
408 ; CHECK-LABEL: @test28(
409 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
410 ; CHECK-NEXT: ret i1 [[CMP]]
411 ;
412 %shr = lshr i8 %x, 7
413 %cmp = icmp ne i8 %shr, 0
414 ret i1 %cmp
415 }
417 define <2 x i1> @test28vec(<2 x i8> %x) {
418 ; CHECK-LABEL: @test28vec(
419 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
420 ; CHECK-NEXT: ret <2 x i1> [[CMP]]
421 ;
422 %shr = lshr <2 x i8> %x, <i8 7, i8 7>
423 %cmp = icmp ne <2 x i8> %shr, zeroinitializer
424 ret <2 x i1> %cmp
425 }
427 define i8 @test28a(i8 %x, i8 %y) {
428 ; CHECK-LABEL: @test28a(
429 ; CHECK-NEXT: entry:
430 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 7
431 ; CHECK-NEXT: [[COND1:%.*]] = icmp slt i8 [[X]], 0
432 ; CHECK-NEXT: br i1 [[COND1]], label [[BB1:%.*]], label [[BB2:%.*]]
433 ; CHECK: bb1:
434 ; CHECK-NEXT: ret i8 [[TMP1]]
435 ; CHECK: bb2:
436 ; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], [[Y:%.*]]
437 ; CHECK-NEXT: ret i8 [[TMP2]]
438 ;
439 entry:
440 ; This shouldn't be transformed.
441 %tmp1 = lshr i8 %x, 7
442 %cond1 = icmp ne i8 %tmp1, 0
443 br i1 %cond1, label %bb1, label %bb2
444 bb1:
445 ret i8 %tmp1
446 bb2:
447 %tmp2 = add i8 %tmp1, %y
448 ret i8 %tmp2
449 }
452 define i32 @test29(i64 %d18) {
453 ; CHECK-LABEL: @test29(
454 ; CHECK-NEXT: entry:
455 ; CHECK-NEXT: [[TMP916:%.*]] = lshr i64 [[D18:%.*]], 63
456 ; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32
457 ; CHECK-NEXT: ret i32 [[TMP10]]
458 ;
459 entry:
460 %tmp916 = lshr i64 %d18, 32
461 %tmp917 = trunc i64 %tmp916 to i32
462 %tmp10 = lshr i32 %tmp917, 31
463 ret i32 %tmp10
464 }
467 define i32 @test30(i32 %A, i32 %B, i32 %C) {
468 ; CHECK-LABEL: @test30(
469 ; CHECK-NEXT: [[X1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
470 ; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], [[C:%.*]]
471 ; CHECK-NEXT: ret i32 [[Z]]
472 ;
473 %X = shl i32 %A, %C
474 %Y = shl i32 %B, %C
475 %Z = and i32 %X, %Y
476 ret i32 %Z
477 }
479 define i32 @test31(i32 %A, i32 %B, i32 %C) {
480 ; CHECK-LABEL: @test31(
481 ; CHECK-NEXT: [[X1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
482 ; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], [[C:%.*]]
483 ; CHECK-NEXT: ret i32 [[Z]]
484 ;
485 %X = lshr i32 %A, %C
486 %Y = lshr i32 %B, %C
487 %Z = or i32 %X, %Y
488 ret i32 %Z
489 }
491 define i32 @test32(i32 %A, i32 %B, i32 %C) {
492 ; CHECK-LABEL: @test32(
493 ; CHECK-NEXT: [[X1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
494 ; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], [[C:%.*]]
495 ; CHECK-NEXT: ret i32 [[Z]]
496 ;
497 %X = ashr i32 %A, %C
498 %Y = ashr i32 %B, %C
499 %Z = xor i32 %X, %Y
500 ret i32 %Z
501 }
503 define i1 @test33(i32 %X) {
504 ; CHECK-LABEL: @test33(
505 ; CHECK-NEXT: [[TMP1_MASK:%.*]] = and i32 [[X:%.*]], 16777216
506 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0
507 ; CHECK-NEXT: ret i1 [[TMP2]]
508 ;
509 %tmp1 = shl i32 %X, 7
510 %tmp2 = icmp slt i32 %tmp1, 0
511 ret i1 %tmp2
512 }
514 define <2 x i1> @test33vec(<2 x i32> %X) {
515 ; CHECK-LABEL: @test33vec(
516 ; CHECK-NEXT: [[TMP1_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 16777216, i32 16777216>
517 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1_MASK]], zeroinitializer
518 ; CHECK-NEXT: ret <2 x i1> [[TMP2]]
519 ;
520 %tmp1 = shl <2 x i32> %X, <i32 7, i32 7>
521 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer
522 ret <2 x i1> %tmp2
523 }
525 define i1 @test34(i32 %X) {
526 ; CHECK-LABEL: @test34(
527 ; CHECK-NEXT: ret i1 false
528 ;
529 %tmp1 = lshr i32 %X, 7
530 %tmp2 = icmp slt i32 %tmp1, 0
531 ret i1 %tmp2
532 }
534 define i1 @test35(i32 %X) {
535 ; CHECK-LABEL: @test35(
536 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[X:%.*]], 0
537 ; CHECK-NEXT: ret i1 [[TMP2]]
538 ;
539 %tmp1 = ashr i32 %X, 7
540 %tmp2 = icmp slt i32 %tmp1, 0
541 ret i1 %tmp2
542 }
544 define <2 x i1> @test35vec(<2 x i32> %X) {
545 ; CHECK-LABEL: @test35vec(
546 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
547 ; CHECK-NEXT: ret <2 x i1> [[TMP2]]
548 ;
549 %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7>
550 %tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer
551 ret <2 x i1> %tmp2
552 }
554 define i128 @test36(i128 %A, i128 %B) {
555 ; CHECK-LABEL: @test36(
556 ; CHECK-NEXT: [[TMP231:%.*]] = or i128 [[B:%.*]], [[A:%.*]]
557 ; CHECK-NEXT: [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615
558 ; CHECK-NEXT: ret i128 [[INS]]
559 ;
560 %tmp27 = shl i128 %A, 64
561 %tmp23 = shl i128 %B, 64
562 %ins = or i128 %tmp23, %tmp27
563 %tmp45 = lshr i128 %ins, 64
564 ret i128 %tmp45
565 }
567 define i64 @test37(i128 %A, i32 %B) {
568 ; CHECK-LABEL: @test37(
569 ; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[B:%.*]] to i128
570 ; CHECK-NEXT: [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32
571 ; CHECK-NEXT: [[INS:%.*]] = or i128 [[TMP23]], [[A:%.*]]
572 ; CHECK-NEXT: [[TMP46:%.*]] = trunc i128 [[INS]] to i64
573 ; CHECK-NEXT: ret i64 [[TMP46]]
574 ;
575 %tmp27 = shl i128 %A, 64
576 %tmp22 = zext i32 %B to i128
577 %tmp23 = shl i128 %tmp22, 96
578 %ins = or i128 %tmp23, %tmp27
579 %tmp45 = lshr i128 %ins, 64
580 %tmp46 = trunc i128 %tmp45 to i64
581 ret i64 %tmp46
582 }
584 define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
585 ; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
586 ; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
587 ; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17>
588 ; CHECK-NEXT: ret <2 x i32> [[T3]]
589 ;
590 %t2 = zext <2 x i8> %x to <2 x i32>
591 %t3 = shl <2 x i32> %t2, <i32 17, i32 17>
592 ret <2 x i32> %t3
593 }
595 define i32 @test38(i32 %x) nounwind readnone {
596 ; CHECK-LABEL: @test38(
597 ; CHECK-NEXT: [[REM1:%.*]] = and i32 [[X:%.*]], 31
598 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]]
599 ; CHECK-NEXT: ret i32 [[SHL]]
600 ;
601 %rem = srem i32 %x, 32
602 %shl = shl i32 1, %rem
603 ret i32 %shl
604 }
606 ; <rdar://problem/8756731>
607 define i8 @test39(i32 %a0) {
608 ; CHECK-LABEL: @test39(
609 ; CHECK-NEXT: entry:
610 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[A0:%.*]] to i8
611 ; CHECK-NEXT: [[TMP5:%.*]] = shl i8 [[TMP4]], 5
612 ; CHECK-NEXT: [[TMP49:%.*]] = shl i8 [[TMP4]], 6
613 ; CHECK-NEXT: [[TMP50:%.*]] = and i8 [[TMP49]], 64
614 ; CHECK-NEXT: [[TMP51:%.*]] = xor i8 [[TMP50]], [[TMP5]]
615 ; CHECK-NEXT: [[TMP0:%.*]] = shl i8 [[TMP4]], 2
616 ; CHECK-NEXT: [[TMP54:%.*]] = and i8 [[TMP0]], 16
617 ; CHECK-NEXT: [[TMP551:%.*]] = or i8 [[TMP54]], [[TMP51]]
618 ; CHECK-NEXT: ret i8 [[TMP551]]
619 ;
620 entry:
621 %tmp4 = trunc i32 %a0 to i8
622 %tmp5 = shl i8 %tmp4, 5
623 %tmp48 = and i8 %tmp5, 32
624 %tmp49 = lshr i8 %tmp48, 5
625 %tmp50 = mul i8 %tmp49, 64
626 %tmp51 = xor i8 %tmp50, %tmp5
627 %tmp52 = and i8 %tmp51, -128
628 %tmp53 = lshr i8 %tmp52, 7
629 %tmp54 = mul i8 %tmp53, 16
630 %tmp55 = xor i8 %tmp54, %tmp51
631 ret i8 %tmp55
632 }
634 ; PR9809
635 define i32 @test40(i32 %a, i32 %b) nounwind {
636 ; CHECK-LABEL: @test40(
637 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], 2
638 ; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[A:%.*]], [[TMP1]]
639 ; CHECK-NEXT: ret i32 [[DIV]]
640 ;
641 %shl1 = shl i32 1, %b
642 %shl2 = shl i32 %shl1, 2
643 %div = udiv i32 %a, %shl2
644 ret i32 %div
645 }
647 define i32 @test41(i32 %a, i32 %b) nounwind {
648 ; CHECK-LABEL: @test41(
649 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 8, [[B:%.*]]
650 ; CHECK-NEXT: ret i32 [[TMP1]]
651 ;
652 %1 = shl i32 1, %b
653 %2 = shl i32 %1, 3
654 ret i32 %2
655 }
657 define i32 @test42(i32 %a, i32 %b) nounwind {
658 ; CHECK-LABEL: @test42(
659 ; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, [[B:%.*]]
660 ; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]]
661 ; CHECK-NEXT: ret i32 [[DIV2]]
662 ;
663 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero
664 %div2 = udiv i32 %a, %div
665 ret i32 %div2
666 }
668 define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) {
669 ; CHECK-LABEL: @test42vec(
670 ; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, [[B:%.*]]
671 ; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> [[A:%.*]], [[DIV]]
672 ; CHECK-NEXT: ret <2 x i32> [[DIV2]]
673 ;
674 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero
675 %div2 = udiv <2 x i32> %a, %div
676 ret <2 x i32> %div2
677 }
679 define i32 @test43(i32 %a, i32 %b) nounwind {
680 ; CHECK-LABEL: @test43(
681 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], 12
682 ; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 [[A:%.*]], [[TMP1]]
683 ; CHECK-NEXT: ret i32 [[DIV2]]
684 ;
685 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero
686 %div2 = udiv i32 %a, %div
687 ret i32 %div2
688 }
690 define i32 @test44(i32 %a) nounwind {
691 ; CHECK-LABEL: @test44(
692 ; CHECK-NEXT: [[Y:%.*]] = shl i32 [[A:%.*]], 5
693 ; CHECK-NEXT: ret i32 [[Y]]
694 ;
695 %y = shl nuw i32 %a, 1
696 %z = shl i32 %y, 4
697 ret i32 %z
698 }
700 define i32 @test45(i32 %a) nounwind {
701 ; CHECK-LABEL: @test45(
702 ; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[A:%.*]], 5
703 ; CHECK-NEXT: ret i32 [[Y]]
704 ;
705 %y = lshr exact i32 %a, 1
706 %z = lshr i32 %y, 4
707 ret i32 %z
708 }
710 ; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
712 define i32 @test46(i32 %a) {
713 ; CHECK-LABEL: @test46(
714 ; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 [[A:%.*]], 2
715 ; CHECK-NEXT: ret i32 [[Z]]
716 ;
717 %y = ashr exact i32 %a, 3
718 %z = shl i32 %y, 1
719 ret i32 %z
720 }
722 ; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
724 define <2 x i32> @test46_splat_vec(<2 x i32> %a) {
725 ; CHECK-LABEL: @test46_splat_vec(
726 ; CHECK-NEXT: [[Z:%.*]] = ashr exact <2 x i32> [[A:%.*]], <i32 2, i32 2>
727 ; CHECK-NEXT: ret <2 x i32> [[Z]]
728 ;
729 %y = ashr exact <2 x i32> %a, <i32 3, i32 3>
730 %z = shl <2 x i32> %y, <i32 1, i32 1>
731 ret <2 x i32> %z
732 }
734 ; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
736 define i8 @test47(i8 %a) {
737 ; CHECK-LABEL: @test47(
738 ; CHECK-NEXT: [[Z:%.*]] = lshr exact i8 [[A:%.*]], 2
739 ; CHECK-NEXT: ret i8 [[Z]]
740 ;
741 %y = lshr exact i8 %a, 3
742 %z = shl i8 %y, 1
743 ret i8 %z
744 }
746 ; (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
748 define <2 x i8> @test47_splat_vec(<2 x i8> %a) {
749 ; CHECK-LABEL: @test47_splat_vec(
750 ; CHECK-NEXT: [[Z:%.*]] = lshr exact <2 x i8> [[A:%.*]], <i8 2, i8 2>
751 ; CHECK-NEXT: ret <2 x i8> [[Z]]
752 ;
753 %y = lshr exact <2 x i8> %a, <i8 3, i8 3>
754 %z = shl <2 x i8> %y, <i8 1, i8 1>
755 ret <2 x i8> %z
756 }
758 ; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1
760 define i32 @test48(i32 %x) {
761 ; CHECK-LABEL: @test48(
762 ; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2
763 ; CHECK-NEXT: ret i32 [[B]]
764 ;
765 %A = lshr exact i32 %x, 1
766 %B = shl i32 %A, 3
767 ret i32 %B
768 }
770 ; Verify that wrap flags are preserved from the original 'shl'.
772 define i32 @test48_nuw_nsw(i32 %x) {
773 ; CHECK-LABEL: @test48_nuw_nsw(
774 ; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2
775 ; CHECK-NEXT: ret i32 [[B]]
776 ;
777 %A = lshr exact i32 %x, 1
778 %B = shl nuw nsw i32 %A, 3
779 ret i32 %B
780 }
782 ; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
784 define <2 x i32> @test48_splat_vec(<2 x i32> %x) {
785 ; CHECK-LABEL: @test48_splat_vec(
786 ; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
787 ; CHECK-NEXT: ret <2 x i32> [[B]]
788 ;
789 %A = lshr exact <2 x i32> %x, <i32 1, i32 1>
790 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
791 ret <2 x i32> %B
792 }
794 ; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1
796 define i32 @test49(i32 %x) {
797 ; CHECK-LABEL: @test49(
798 ; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2
799 ; CHECK-NEXT: ret i32 [[B]]
800 ;
801 %A = ashr exact i32 %x, 1
802 %B = shl i32 %A, 3
803 ret i32 %B
804 }
806 ; Verify that wrap flags are preserved from the original 'shl'.
808 define i32 @test49_nuw_nsw(i32 %x) {
809 ; CHECK-LABEL: @test49_nuw_nsw(
810 ; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2
811 ; CHECK-NEXT: ret i32 [[B]]
812 ;
813 %A = ashr exact i32 %x, 1
814 %B = shl nuw nsw i32 %A, 3
815 ret i32 %B
816 }
818 ; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
820 define <2 x i32> @test49_splat_vec(<2 x i32> %x) {
821 ; CHECK-LABEL: @test49_splat_vec(
822 ; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
823 ; CHECK-NEXT: ret <2 x i32> [[B]]
824 ;
825 %A = ashr exact <2 x i32> %x, <i32 1, i32 1>
826 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
827 ret <2 x i32> %B
828 }
830 ; (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
832 define i32 @test50(i32 %x) {
833 ; CHECK-LABEL: @test50(
834 ; CHECK-NEXT: [[B:%.*]] = ashr i32 [[X:%.*]], 2
835 ; CHECK-NEXT: ret i32 [[B]]
836 ;
837 %A = shl nsw i32 %x, 1
838 %B = ashr i32 %A, 3
839 ret i32 %B
840 }
842 ; (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
843 ; Also, check that exact is propagated.
845 define <2 x i32> @test50_splat_vec(<2 x i32> %x) {
846 ; CHECK-LABEL: @test50_splat_vec(
847 ; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i32> [[X:%.*]], <i32 2, i32 2>
848 ; CHECK-NEXT: ret <2 x i32> [[B]]
849 ;
850 %A = shl nsw <2 x i32> %x, <i32 1, i32 1>
851 %B = ashr exact <2 x i32> %A, <i32 3, i32 3>
852 ret <2 x i32> %B
853 }
855 ; (X <<nuw C1) >>u C2 --> X >>u (C2-C1)
857 define i32 @test51(i32 %x) {
858 ; CHECK-LABEL: @test51(
859 ; CHECK-NEXT: [[B:%.*]] = lshr i32 [[X:%.*]], 2
860 ; CHECK-NEXT: ret i32 [[B]]
861 ;
862 %A = shl nuw i32 %x, 1
863 %B = lshr i32 %A, 3
864 ret i32 %B
865 }
867 ; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats
868 ; Also, check that exact is propagated.
870 define <2 x i32> @test51_splat_vec(<2 x i32> %x) {
871 ; CHECK-LABEL: @test51_splat_vec(
872 ; CHECK-NEXT: [[B:%.*]] = lshr exact <2 x i32> [[X:%.*]], <i32 2, i32 2>
873 ; CHECK-NEXT: ret <2 x i32> [[B]]
874 ;
875 %A = shl nuw <2 x i32> %x, <i32 1, i32 1>
876 %B = lshr exact <2 x i32> %A, <i32 3, i32 3>
877 ret <2 x i32> %B
878 }
880 ; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2)
881 ; Also, check that exact is propagated.
883 define i32 @test51_no_nuw(i32 %x) {
884 ; CHECK-LABEL: @test51_no_nuw(
885 ; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[X:%.*]], 2
886 ; CHECK-NEXT: [[B:%.*]] = and i32 [[TMP1]], 536870911
887 ; CHECK-NEXT: ret i32 [[B]]
888 ;
889 %A = shl i32 %x, 1
890 %B = lshr exact i32 %A, 3
891 ret i32 %B
892 }
894 ; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2)
896 define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) {
897 ; CHECK-LABEL: @test51_no_nuw_splat_vec(
898 ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2>
899 ; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911>
900 ; CHECK-NEXT: ret <2 x i32> [[B]]
901 ;
902 %A = shl <2 x i32> %x, <i32 1, i32 1>
903 %B = lshr <2 x i32> %A, <i32 3, i32 3>
904 ret <2 x i32> %B
905 }
907 ; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2)
909 define i32 @test52(i32 %x) {
910 ; CHECK-LABEL: @test52(
911 ; CHECK-NEXT: [[B:%.*]] = shl nsw i32 [[X:%.*]], 2
912 ; CHECK-NEXT: ret i32 [[B]]
913 ;
914 %A = shl nsw i32 %x, 3
915 %B = ashr i32 %A, 1
916 ret i32 %B
917 }
919 ; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2)
921 define <2 x i32> @test52_splat_vec(<2 x i32> %x) {
922 ; CHECK-LABEL: @test52_splat_vec(
923 ; CHECK-NEXT: [[B:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
924 ; CHECK-NEXT: ret <2 x i32> [[B]]
925 ;
926 %A = shl nsw <2 x i32> %x, <i32 3, i32 3>
927 %B = ashr <2 x i32> %A, <i32 1, i32 1>
928 ret <2 x i32> %B
929 }
931 ; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2)
933 define i32 @test53(i32 %x) {
934 ; CHECK-LABEL: @test53(
935 ; CHECK-NEXT: [[B:%.*]] = shl nuw i32 [[X:%.*]], 2
936 ; CHECK-NEXT: ret i32 [[B]]
937 ;
938 %A = shl nuw i32 %x, 3
939 %B = lshr i32 %A, 1
940 ret i32 %B
941 }
943 ; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2)
945 define <2 x i32> @test53_splat_vec(<2 x i32> %x) {
946 ; CHECK-LABEL: @test53_splat_vec(
947 ; CHECK-NEXT: [[B:%.*]] = shl nuw <2 x i32> [[X:%.*]], <i32 2, i32 2>
948 ; CHECK-NEXT: ret <2 x i32> [[B]]
949 ;
950 %A = shl nuw <2 x i32> %x, <i32 3, i32 3>
951 %B = lshr <2 x i32> %A, <i32 1, i32 1>
952 ret <2 x i32> %B
953 }
955 ; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2)
957 define i8 @test53_no_nuw(i8 %x) {
958 ; CHECK-LABEL: @test53_no_nuw(
959 ; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X:%.*]], 2
960 ; CHECK-NEXT: [[B:%.*]] = and i8 [[TMP1]], 124
961 ; CHECK-NEXT: ret i8 [[B]]
962 ;
963 %A = shl i8 %x, 3
964 %B = lshr i8 %A, 1
965 ret i8 %B
966 }
968 ; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2)
970 define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) {
971 ; CHECK-LABEL: @test53_no_nuw_splat_vec(
972 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 2, i8 2>
973 ; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124>
974 ; CHECK-NEXT: ret <2 x i8> [[B]]
975 ;
976 %A = shl <2 x i8> %x, <i8 3, i8 3>
977 %B = lshr <2 x i8> %A, <i8 1, i8 1>
978 ret <2 x i8> %B
979 }
981 define i32 @test54(i32 %x) {
982 ; CHECK-LABEL: @test54(
983 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
984 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16
985 ; CHECK-NEXT: ret i32 [[AND]]
986 ;
987 %shr2 = lshr i32 %x, 1
988 %shl = shl i32 %shr2, 4
989 %and = and i32 %shl, 16
990 ret i32 %and
991 }
993 define <2 x i32> @test54_splat_vec(<2 x i32> %x) {
994 ; CHECK-LABEL: @test54_splat_vec(
995 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 3, i32 3>
996 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16>
997 ; CHECK-NEXT: ret <2 x i32> [[AND]]
998 ;
999 %shr2 = lshr <2 x i32> %x, <i32 1, i32 1>
1000 %shl = shl <2 x i32> %shr2, <i32 4, i32 4>
1001 %and = and <2 x i32> %shl, <i32 16, i32 16>
1002 ret <2 x i32> %and
1003 }
1005 define i32 @test55(i32 %x) {
1006 ; CHECK-LABEL: @test55(
1007 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
1008 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8
1009 ; CHECK-NEXT: ret i32 [[OR]]
1010 ;
1011 %shr2 = lshr i32 %x, 1
1012 %shl = shl i32 %shr2, 4
1013 %or = or i32 %shl, 8
1014 ret i32 %or
1015 }
1017 define i32 @test56(i32 %x) {
1018 ; CHECK-LABEL: @test56(
1019 ; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 [[X:%.*]], 1
1020 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[SHR2]], 4
1021 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7
1022 ; CHECK-NEXT: ret i32 [[OR]]
1023 ;
1024 %shr2 = lshr i32 %x, 1
1025 %shl = shl i32 %shr2, 4
1026 %or = or i32 %shl, 7
1027 ret i32 %or
1028 }
1030 define i32 @test57(i32 %x) {
1031 ; CHECK-LABEL: @test57(
1032 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1033 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[TMP1]], 4
1034 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7
1035 ; CHECK-NEXT: ret i32 [[OR]]
1036 ;
1037 %shr = ashr i32 %x, 1
1038 %shl = shl i32 %shr, 4
1039 %or = or i32 %shl, 7
1040 ret i32 %or
1041 }
1043 define i32 @test58(i32 %x) {
1044 ; CHECK-LABEL: @test58(
1045 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3
1046 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1
1047 ; CHECK-NEXT: ret i32 [[OR]]
1048 ;
1049 %shr = ashr i32 %x, 4
1050 %shl = shl i32 %shr, 1
1051 %or = or i32 %shl, 1
1052 ret i32 %or
1053 }
1055 define <2 x i32> @test58_splat_vec(<2 x i32> %x) {
1056 ; CHECK-LABEL: @test58_splat_vec(
1057 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 3, i32 3>
1058 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
1059 ; CHECK-NEXT: ret <2 x i32> [[OR]]
1060 ;
1061 %shr = ashr <2 x i32> %x, <i32 4, i32 4>
1062 %shl = shl <2 x i32> %shr, <i32 1, i32 1>
1063 %or = or <2 x i32> %shl, <i32 1, i32 1>
1064 ret <2 x i32> %or
1065 }
1067 define i32 @test59(i32 %x) {
1068 ; CHECK-LABEL: @test59(
1069 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[X:%.*]], 4
1070 ; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SHR]], 1
1071 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2
1072 ; CHECK-NEXT: ret i32 [[OR]]
1073 ;
1074 %shr = ashr i32 %x, 4
1075 %shl = shl i32 %shr, 1
1076 %or = or i32 %shl, 2
1077 ret i32 %or
1078 }
1080 ; propagate "exact" trait
1081 define i32 @test60(i32 %x) {
1082 ; CHECK-LABEL: @test60(
1083 ; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 [[X:%.*]], 3
1084 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1
1085 ; CHECK-NEXT: ret i32 [[OR]]
1086 ;
1087 %shr = ashr exact i32 %x, 4
1088 %shl = shl i32 %shr, 1
1089 %or = or i32 %shl, 1
1090 ret i32 %or
1091 }
1093 ; PR17026
1094 define void @test61(i128 %arg) {
1095 ; CHECK-LABEL: @test61(
1096 ; CHECK-NEXT: bb:
1097 ; CHECK-NEXT: br i1 undef, label [[BB1:%.*]], label [[BB12:%.*]]
1098 ; CHECK: bb1:
1099 ; CHECK-NEXT: br label [[BB2:%.*]]
1100 ; CHECK: bb2:
1101 ; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB7:%.*]]
1102 ; CHECK: bb3:
1103 ; CHECK-NEXT: br label [[BB8:%.*]]
1104 ; CHECK: bb7:
1105 ; CHECK-NEXT: br i1 undef, label [[BB8]], label [[BB2]]
1106 ; CHECK: bb8:
1107 ; CHECK-NEXT: br i1 undef, label [[BB11:%.*]], label [[BB12]]
1108 ; CHECK: bb11:
1109 ; CHECK-NEXT: br i1 undef, label [[BB1]], label [[BB12]]
1110 ; CHECK: bb12:
1111 ; CHECK-NEXT: ret void
1112 ;
1113 bb:
1114 br i1 undef, label %bb1, label %bb12
1116 bb1: ; preds = %bb11, %bb
1117 br label %bb2
1119 bb2: ; preds = %bb7, %bb1
1120 br i1 undef, label %bb3, label %bb7
1122 bb3: ; preds = %bb2
1123 %tmp = lshr i128 %arg, 36893488147419103232
1124 %tmp4 = shl i128 %tmp, 0
1125 %tmp5 = or i128 %tmp4, undef
1126 %tmp6 = trunc i128 %tmp5 to i16
1127 br label %bb8
1129 bb7: ; preds = %bb2
1130 br i1 undef, label %bb8, label %bb2
1132 bb8: ; preds = %bb7, %bb3
1133 %tmp9 = phi i16 [ %tmp6, %bb3 ], [ undef, %bb7 ]
1134 %tmp10 = icmp eq i16 %tmp9, 0
1135 br i1 %tmp10, label %bb11, label %bb12
1137 bb11: ; preds = %bb8
1138 br i1 undef, label %bb1, label %bb12
1140 bb12: ; preds = %bb11, %bb8, %bb
1141 ret void
1142 }
1144 define i32 @test62(i32 %a) {
1145 ; CHECK-LABEL: @test62(
1146 ; CHECK-NEXT: ret i32 undef
1147 ;
1148 %b = ashr i32 %a, 32 ; shift all bits out
1149 ret i32 %b
1150 }
1152 define <4 x i32> @test62_splat_vector(<4 x i32> %a) {
1153 ; CHECK-LABEL: @test62_splat_vector(
1154 ; CHECK-NEXT: ret <4 x i32> undef
1155 ;
1156 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out
1157 ret <4 x i32> %b
1158 }
1160 define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) {
1161 ; CHECK-LABEL: @test62_non_splat_vector(
1162 ; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 32, i32 0, i32 1, i32 2>
1163 ; CHECK-NEXT: ret <4 x i32> [[B]]
1164 ;
1165 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out
1166 ret <4 x i32> %b
1167 }
1169 define <2 x i65> @test_63(<2 x i64> %t) {
1170 ; CHECK-LABEL: @test_63(
1171 ; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> [[T:%.*]] to <2 x i65>
1172 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33>
1173 ; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33>
1174 ; CHECK-NEXT: ret <2 x i65> [[B]]
1175 ;
1176 %a = zext <2 x i64> %t to <2 x i65>
1177 %sext = shl <2 x i65> %a, <i65 33, i65 33>
1178 %b = ashr <2 x i65> %sext, <i65 33, i65 33>
1179 ret <2 x i65> %b
1180 }
1182 define i32 @test_shl_zext_bool(i1 %t) {
1183 ; CHECK-LABEL: @test_shl_zext_bool(
1184 ; CHECK-NEXT: [[SHL:%.*]] = select i1 [[T:%.*]], i32 4, i32 0
1185 ; CHECK-NEXT: ret i32 [[SHL]]
1186 ;
1187 %ext = zext i1 %t to i32
1188 %shl = shl i32 %ext, 2
1189 ret i32 %shl
1190 }
1192 define <2 x i32> @test_shl_zext_bool_splat(<2 x i1> %t) {
1193 ; CHECK-LABEL: @test_shl_zext_bool_splat(
1194 ; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 8, i32 8>, <2 x i32> zeroinitializer
1195 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
1196 ;
1197 %ext = zext <2 x i1> %t to <2 x i32>
1198 %shl = shl <2 x i32> %ext, <i32 3, i32 3>
1199 ret <2 x i32> %shl
1200 }
1202 define <2 x i32> @test_shl_zext_bool_vec(<2 x i1> %t) {
1203 ; CHECK-LABEL: @test_shl_zext_bool_vec(
1204 ; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 4, i32 8>, <2 x i32> zeroinitializer
1205 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
1206 ;
1207 %ext = zext <2 x i1> %t to <2 x i32>
1208 %shl = shl <2 x i32> %ext, <i32 2, i32 3>
1209 ret <2 x i32> %shl
1210 }
1212 define i32 @test_shl_zext_bool_not_constant(i1 %cmp, i32 %shamt) {
1213 ; CHECK-LABEL: @test_shl_zext_bool_not_constant(
1214 ; CHECK-NEXT: [[CONV3:%.*]] = zext i1 [[CMP:%.*]] to i32
1215 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV3]], [[SHAMT:%.*]]
1216 ; CHECK-NEXT: ret i32 [[SHL]]
1217 ;
1218 %conv3 = zext i1 %cmp to i32
1219 %shl = shl i32 %conv3, %shamt
1220 ret i32 %shl
1221 }
1223 define i64 @shl_zext(i32 %t) {
1224 ; CHECK-LABEL: @shl_zext(
1225 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[T:%.*]], 8
1226 ; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64
1227 ; CHECK-NEXT: ret i64 [[SHL]]
1228 ;
1229 %and = and i32 %t, 16777215
1230 %ext = zext i32 %and to i64
1231 %shl = shl i64 %ext, 8
1232 ret i64 %shl
1233 }
1235 declare void @use(i64)
1237 define i64 @shl_zext_extra_use(i32 %t) {
1238 ; CHECK-LABEL: @shl_zext_extra_use(
1239 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[T:%.*]], 16777215
1240 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[AND]] to i64
1241 ; CHECK-NEXT: call void @use(i64 [[EXT]])
1242 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 8
1243 ; CHECK-NEXT: ret i64 [[SHL]]
1244 ;
1245 %and = and i32 %t, 16777215
1246 %ext = zext i32 %and to i64
1247 call void @use(i64 %ext)
1248 %shl = shl i64 %ext, 8
1249 ret i64 %shl
1250 }
1253 define <2 x i64> @shl_zext_splat_vec(<2 x i32> %t) {
1254 ; CHECK-LABEL: @shl_zext_splat_vec(
1255 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[T:%.*]], <i32 8, i32 8>
1256 ; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
1257 ; CHECK-NEXT: ret <2 x i64> [[SHL]]
1258 ;
1259 %and = and <2 x i32> %t, <i32 16777215, i32 16777215>
1260 %ext = zext <2 x i32> %and to <2 x i64>
1261 %shl = shl <2 x i64> %ext, <i64 8, i64 8>
1262 ret <2 x i64> %shl
1263 }
1265 define i64 @shl_zext_mul(i32 %t) {
1266 ; CHECK-LABEL: @shl_zext_mul(
1267 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215
1268 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64
1269 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32
1270 ; CHECK-NEXT: ret i64 [[SHL]]
1271 ;
1272 %mul = mul i32 %t, 16777215
1273 %ext = zext i32 %mul to i64
1274 %shl = shl i64 %ext, 32
1275 ret i64 %shl
1276 }
1278 define <3 x i17> @shl_zext_mul_splat(<3 x i5> %t) {
1279 ; CHECK-LABEL: @shl_zext_mul_splat(
1280 ; CHECK-NEXT: [[MUL:%.*]] = mul <3 x i5> [[T:%.*]], <i5 13, i5 13, i5 13>
1281 ; CHECK-NEXT: [[EXT:%.*]] = zext <3 x i5> [[MUL]] to <3 x i17>
1282 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw <3 x i17> [[EXT]], <i17 12, i17 12, i17 12>
1283 ; CHECK-NEXT: ret <3 x i17> [[SHL]]
1284 ;
1285 %mul = mul <3 x i5> %t, <i5 13, i5 13, i5 13>
1286 %ext = zext <3 x i5> %mul to <3 x i17>
1287 %shl = shl <3 x i17> %ext, <i17 12, i17 12, i17 12>
1288 ret <3 x i17> %shl
1289 }
1291 define i64 @shl_zext_mul_low_shift_amount(i32 %t) {
1292 ; CHECK-LABEL: @shl_zext_mul_low_shift_amount(
1293 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215
1294 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64
1295 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 31
1296 ; CHECK-NEXT: ret i64 [[SHL]]
1297 ;
1298 %mul = mul i32 %t, 16777215
1299 %ext = zext i32 %mul to i64
1300 %shl = shl i64 %ext, 31
1301 ret i64 %shl
1302 }
1304 define i64 @shl_zext_mul_extra_use1(i32 %t) {
1305 ; CHECK-LABEL: @shl_zext_mul_extra_use1(
1306 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215
1307 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64
1308 ; CHECK-NEXT: call void @use(i64 [[EXT]])
1309 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32
1310 ; CHECK-NEXT: ret i64 [[SHL]]
1311 ;
1312 %mul = mul i32 %t, 16777215
1313 %ext = zext i32 %mul to i64
1314 call void @use(i64 %ext)
1315 %shl = shl i64 %ext, 32
1316 ret i64 %shl
1317 }
1319 declare void @use_i32(i32)
1321 define i64 @shl_zext_mul_extra_use2(i32 %t) {
1322 ; CHECK-LABEL: @shl_zext_mul_extra_use2(
1323 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215
1324 ; CHECK-NEXT: call void @use_i32(i32 [[MUL]])
1325 ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64
1326 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32
1327 ; CHECK-NEXT: ret i64 [[SHL]]
1328 ;
1329 %mul = mul i32 %t, 16777215
1330 call void @use_i32(i32 %mul)
1331 %ext = zext i32 %mul to i64
1332 %shl = shl i64 %ext, 32
1333 ret i64 %shl
1334 }
1336 define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
1337 ; CHECK-LABEL: @ashr_demanded_bits_splat(
1338 ; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
1339 ; CHECK-NEXT: ret <2 x i8> [[SHR]]
1340 ;
1341 %and = and <2 x i8> %x, <i8 128, i8 128>
1342 %shr = ashr <2 x i8> %and, <i8 7, i8 7>
1343 ret <2 x i8> %shr
1344 }
1346 define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
1347 ; CHECK-LABEL: @lshr_demanded_bits_splat(
1348 ; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 7, i8 7>
1349 ; CHECK-NEXT: ret <2 x i8> [[SHR]]
1350 ;
1351 %and = and <2 x i8> %x, <i8 128, i8 128>
1352 %shr = lshr <2 x i8> %and, <i8 7, i8 7>
1353 ret <2 x i8> %shr
1354 }
1356 ; Make sure known bits works correctly with non power of 2 bit widths.
1357 define i7 @test65(i7 %a, i7 %b) {
1358 ; CHECK-LABEL: @test65(
1359 ; CHECK-NEXT: ret i7 0
1360 ;
1361 %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width.
1362 %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit.
1363 %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0.
1364 ret i7 %y
1365 }
1367 define i32 @shl_select_add_true(i32 %x, i1 %cond) {
1368 ; CHECK-LABEL: @shl_select_add_true(
1369 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1370 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
1371 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1372 ; CHECK-NEXT: ret i32 [[TMP3]]
1373 ;
1374 %1 = add i32 %x, 7
1375 %2 = select i1 %cond, i32 %1, i32 %x
1376 %3 = shl i32 %2, 1
1377 ret i32 %3
1378 }
1380 define i32 @shl_select_add_false(i32 %x, i1 %cond) {
1381 ; CHECK-LABEL: @shl_select_add_false(
1382 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1383 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14
1384 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1385 ; CHECK-NEXT: ret i32 [[TMP3]]
1386 ;
1387 %1 = add i32 %x, 7
1388 %2 = select i1 %cond, i32 %x, i32 %1
1389 %3 = shl i32 %2, 1
1390 ret i32 %3
1391 }
1393 define i32 @shl_select_and_true(i32 %x, i1 %cond) {
1394 ; CHECK-LABEL: @shl_select_and_true(
1395 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1396 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
1397 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1398 ; CHECK-NEXT: ret i32 [[TMP3]]
1399 ;
1400 %1 = and i32 %x, 7
1401 %2 = select i1 %cond, i32 %1, i32 %x
1402 %3 = shl i32 %2, 1
1403 ret i32 %3
1404 }
1406 define i32 @shl_select_and_false(i32 %x, i1 %cond) {
1407 ; CHECK-LABEL: @shl_select_and_false(
1408 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1409 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14
1410 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1411 ; CHECK-NEXT: ret i32 [[TMP3]]
1412 ;
1413 %1 = and i32 %x, 7
1414 %2 = select i1 %cond, i32 %x, i32 %1
1415 %3 = shl i32 %2, 1
1416 ret i32 %3
1417 }
1419 define i32 @lshr_select_and_true(i32 %x, i1 %cond) {
1420 ; CHECK-LABEL: @lshr_select_and_true(
1421 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1422 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
1423 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1424 ; CHECK-NEXT: ret i32 [[TMP3]]
1425 ;
1426 %1 = and i32 %x, 7
1427 %2 = select i1 %cond, i32 %1, i32 %x
1428 %3 = lshr i32 %2, 1
1429 ret i32 %3
1430 }
1432 define i32 @lshr_select_and_false(i32 %x, i1 %cond) {
1433 ; CHECK-LABEL: @lshr_select_and_false(
1434 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1435 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3
1436 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1437 ; CHECK-NEXT: ret i32 [[TMP3]]
1438 ;
1439 %1 = and i32 %x, 7
1440 %2 = select i1 %cond, i32 %x, i32 %1
1441 %3 = lshr i32 %2, 1
1442 ret i32 %3
1443 }
1445 define i32 @ashr_select_and_true(i32 %x, i1 %cond) {
1446 ; CHECK-LABEL: @ashr_select_and_true(
1447 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1448 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
1449 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1450 ; CHECK-NEXT: ret i32 [[TMP3]]
1451 ;
1452 %1 = and i32 %x, 2147483655
1453 %2 = select i1 %cond, i32 %1, i32 %x
1454 %3 = ashr i32 %2, 1
1455 ret i32 %3
1456 }
1458 define i32 @ashr_select_and_false(i32 %x, i1 %cond) {
1459 ; CHECK-LABEL: @ashr_select_and_false(
1460 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1461 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821
1462 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1463 ; CHECK-NEXT: ret i32 [[TMP3]]
1464 ;
1465 %1 = and i32 %x, 2147483655
1466 %2 = select i1 %cond, i32 %x, i32 %1
1467 %3 = ashr i32 %2, 1
1468 ret i32 %3
1469 }
1471 define i32 @shl_select_or_true(i32 %x, i1 %cond) {
1472 ; CHECK-LABEL: @shl_select_or_true(
1473 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1474 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
1475 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1476 ; CHECK-NEXT: ret i32 [[TMP3]]
1477 ;
1478 %1 = or i32 %x, 7
1479 %2 = select i1 %cond, i32 %1, i32 %x
1480 %3 = shl i32 %2, 1
1481 ret i32 %3
1482 }
1484 define i32 @shl_select_or_false(i32 %x, i1 %cond) {
1485 ; CHECK-LABEL: @shl_select_or_false(
1486 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1487 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14
1488 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1489 ; CHECK-NEXT: ret i32 [[TMP3]]
1490 ;
1491 %1 = or i32 %x, 7
1492 %2 = select i1 %cond, i32 %x, i32 %1
1493 %3 = shl i32 %2, 1
1494 ret i32 %3
1495 }
1497 define i32 @lshr_select_or_true(i32 %x, i1 %cond) {
1498 ; CHECK-LABEL: @lshr_select_or_true(
1499 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1500 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
1501 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1502 ; CHECK-NEXT: ret i32 [[TMP3]]
1503 ;
1504 %1 = or i32 %x, 7
1505 %2 = select i1 %cond, i32 %1, i32 %x
1506 %3 = lshr i32 %2, 1
1507 ret i32 %3
1508 }
1510 define i32 @lshr_select_or_false(i32 %x, i1 %cond) {
1511 ; CHECK-LABEL: @lshr_select_or_false(
1512 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1513 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
1514 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1515 ; CHECK-NEXT: ret i32 [[TMP3]]
1516 ;
1517 %1 = or i32 %x, 7
1518 %2 = select i1 %cond, i32 %x, i32 %1
1519 %3 = lshr i32 %2, 1
1520 ret i32 %3
1521 }
1523 define i32 @ashr_select_or_true(i32 %x, i1 %cond) {
1524 ; CHECK-LABEL: @ashr_select_or_true(
1525 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1526 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
1527 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1528 ; CHECK-NEXT: ret i32 [[TMP3]]
1529 ;
1530 %1 = or i32 %x, 7
1531 %2 = select i1 %cond, i32 %1, i32 %x
1532 %3 = ashr i32 %2, 1
1533 ret i32 %3
1534 }
1536 define i32 @ashr_select_or_false(i32 %x, i1 %cond) {
1537 ; CHECK-LABEL: @ashr_select_or_false(
1538 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1539 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3
1540 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1541 ; CHECK-NEXT: ret i32 [[TMP3]]
1542 ;
1543 %1 = or i32 %x, 7
1544 %2 = select i1 %cond, i32 %x, i32 %1
1545 %3 = ashr i32 %2, 1
1546 ret i32 %3
1547 }
1549 define i32 @shl_select_xor_true(i32 %x, i1 %cond) {
1550 ; CHECK-LABEL: @shl_select_xor_true(
1551 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1552 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
1553 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1554 ; CHECK-NEXT: ret i32 [[TMP3]]
1555 ;
1556 %1 = xor i32 %x, 7
1557 %2 = select i1 %cond, i32 %1, i32 %x
1558 %3 = shl i32 %2, 1
1559 ret i32 %3
1560 }
1562 define i32 @shl_select_xor_false(i32 %x, i1 %cond) {
1563 ; CHECK-LABEL: @shl_select_xor_false(
1564 ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
1565 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14
1566 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1567 ; CHECK-NEXT: ret i32 [[TMP3]]
1568 ;
1569 %1 = xor i32 %x, 7
1570 %2 = select i1 %cond, i32 %x, i32 %1
1571 %3 = shl i32 %2, 1
1572 ret i32 %3
1573 }
1575 define i32 @lshr_select_xor_true(i32 %x, i1 %cond) {
1576 ; CHECK-LABEL: @lshr_select_xor_true(
1577 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1578 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
1579 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1580 ; CHECK-NEXT: ret i32 [[TMP3]]
1581 ;
1582 %1 = xor i32 %x, 7
1583 %2 = select i1 %cond, i32 %1, i32 %x
1584 %3 = lshr i32 %2, 1
1585 ret i32 %3
1586 }
1588 define i32 @lshr_select_xor_false(i32 %x, i1 %cond) {
1589 ; CHECK-LABEL: @lshr_select_xor_false(
1590 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
1591 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
1592 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1593 ; CHECK-NEXT: ret i32 [[TMP3]]
1594 ;
1595 %1 = xor i32 %x, 7
1596 %2 = select i1 %cond, i32 %x, i32 %1
1597 %3 = lshr i32 %2, 1
1598 ret i32 %3
1599 }
1601 define i32 @ashr_select_xor_true(i32 %x, i1 %cond) {
1602 ; CHECK-LABEL: @ashr_select_xor_true(
1603 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1604 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
1605 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
1606 ; CHECK-NEXT: ret i32 [[TMP3]]
1607 ;
1608 %1 = xor i32 %x, 7
1609 %2 = select i1 %cond, i32 %1, i32 %x
1610 %3 = ashr i32 %2, 1
1611 ret i32 %3
1612 }
1614 define i32 @ashr_select_xor_false(i32 %x, i1 %cond) {
1615 ; CHECK-LABEL: @ashr_select_xor_false(
1616 ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1
1617 ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3
1618 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]]
1619 ; CHECK-NEXT: ret i32 [[TMP3]]
1620 ;
1621 %1 = xor i32 %x, 7
1622 %2 = select i1 %cond, i32 %x, i32 %1
1623 %3 = ashr i32 %2, 1
1624 ret i32 %3
1625 }
1627 ; OSS Fuzz #4871
1628 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4871
1629 define i177 @lshr_out_of_range(i177 %Y, i177** %A2) {
1630 ; CHECK-LABEL: @lshr_out_of_range(
1631 ; CHECK-NEXT: store i177** [[A2:%.*]], i177*** undef, align 8
1632 ; CHECK-NEXT: ret i177 0
1633 ;
1634 %B5 = udiv i177 %Y, -1
1635 %B4 = add i177 %B5, -1
1636 %B2 = add i177 %B4, -1
1637 %B6 = mul i177 %B5, %B2
1638 %B3 = add i177 %B2, %B2
1639 %B10 = sub i177 %B5, %B3
1640 %B12 = lshr i177 %Y, %B6
1641 %C8 = icmp ugt i177 %B12, %B4
1642 %G18 = getelementptr i177*, i177** %A2, i1 %C8
1643 store i177** %G18, i177*** undef
1644 %B1 = udiv i177 %B10, %B6
1645 ret i177 %B1
1646 }
1648 ; OSS Fuzz #5032
1649 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5032
1650 define void @ashr_out_of_range(i177* %A) {
1651 ; CHECK-LABEL: @ashr_out_of_range(
1652 ; CHECK-NEXT: ret void
1653 ;
1654 %L = load i177, i177* %A
1655 %B5 = udiv i177 %L, -1
1656 %B4 = add i177 %B5, -1
1657 %B2 = add i177 %B4, -1
1658 %G11 = getelementptr i177, i177* %A, i177 %B2
1659 %L7 = load i177, i177* %G11
1660 %B6 = mul i177 %B5, %B2
1661 %B24 = ashr i177 %L7, %B6
1662 %B36 = and i177 %L7, %B4
1663 %C17 = icmp sgt i177 %B36, %B24
1664 %G62 = getelementptr i177, i177* %G11, i1 %C17
1665 %B28 = urem i177 %B24, %B6
1666 store i177 %B28, i177* %G62
1667 ret void
1668 }