[InstCombine] Signed saturation patterns
[llvm-complete.git] / test / tools / llvm-exegesis / AArch64 / latency-by-opcode-name.s
blob1d719ce1609dd4c0509d30c142d468b7e4cdea9a
1 # RUN: llvm-exegesis -mode=latency -opcode-name=ADDXrr | FileCheck %s
3 CHECK: ---
4 CHECK-NEXT: mode: latency
5 CHECK-NEXT: key:
6 CHECK-NEXT: instructions:
7 CHECK-NEXT: ADDXrr [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] [[REG3:X[0-9]+|LR]]
8 CHECK-NEXT: config: ''
9 CHECK-NEXT: register_initial_values:
10 CHECK-DAG: - '[[REG2]]=0x0'
11 # We don't check REG3 because in the case that REG2=REG3 the check would fail
12 CHECK-LAST: ...