1 import("//llvm/utils/TableGen/tablegen.gni")
3 tablegen("AMDGPUGenAsmMatcher") {
4 visibility = [ ":LLVMAMDGPUCodeGen" ]
5 args = [ "-gen-asm-matcher" ]
9 tablegen("AMDGPUGenCallingConv") {
10 visibility = [ ":LLVMAMDGPUCodeGen" ]
11 args = [ "-gen-callingconv" ]
15 tablegen("AMDGPUGenDAGISel") {
16 visibility = [ ":LLVMAMDGPUCodeGen" ]
17 args = [ "-gen-dag-isel" ]
21 tablegen("AMDGPUGenGlobalISel") {
22 visibility = [ ":LLVMAMDGPUCodeGen" ]
23 args = [ "-gen-global-isel" ]
24 td_file = "AMDGPUGISel.td"
27 tablegen("AMDGPUGenMCPseudoLowering") {
28 visibility = [ ":LLVMAMDGPUCodeGen" ]
29 args = [ "-gen-pseudo-lowering" ]
33 tablegen("AMDGPUGenRegisterBank") {
34 visibility = [ ":LLVMAMDGPUCodeGen" ]
35 args = [ "-gen-register-bank" ]
39 tablegen("R600GenCallingConv") {
40 visibility = [ ":LLVMAMDGPUCodeGen" ]
41 args = [ "-gen-callingconv" ]
45 tablegen("R600GenDAGISel") {
46 visibility = [ ":LLVMAMDGPUCodeGen" ]
47 args = [ "-gen-dag-isel" ]
51 tablegen("R600GenDFAPacketizer") {
52 visibility = [ ":LLVMAMDGPUCodeGen" ]
53 args = [ "-gen-dfa-packetizer" ]
57 static_library("LLVMAMDGPUCodeGen") {
59 ":AMDGPUGenAsmMatcher",
60 ":AMDGPUGenCallingConv",
62 ":AMDGPUGenGlobalISel",
63 ":AMDGPUGenMCPseudoLowering",
64 ":AMDGPUGenRegisterBank",
65 ":R600GenCallingConv",
67 ":R600GenDFAPacketizer",
71 "//llvm/lib/Analysis",
73 "//llvm/lib/CodeGen/AsmPrinter",
74 "//llvm/lib/CodeGen/GlobalISel",
75 "//llvm/lib/CodeGen/MIRParser",
76 "//llvm/lib/CodeGen/SelectionDAG",
81 "//llvm/lib/Transforms/IPO",
82 "//llvm/lib/Transforms/Scalar",
83 "//llvm/lib/Transforms/Utils",
85 include_dirs = [ "." ]
87 "AMDGPUAliasAnalysis.cpp",
88 "AMDGPUAlwaysInlinePass.cpp",
89 "AMDGPUAnnotateKernelFeatures.cpp",
90 "AMDGPUAnnotateUniformValues.cpp",
91 "AMDGPUArgumentUsageInfo.cpp",
92 "AMDGPUAsmPrinter.cpp",
93 "AMDGPUAtomicOptimizer.cpp",
94 "AMDGPUCallLowering.cpp",
95 "AMDGPUCodeGenPrepare.cpp",
96 "AMDGPUFixFunctionBitcasts.cpp",
97 "AMDGPUFrameLowering.cpp",
98 "AMDGPUHSAMetadataStreamer.cpp",
99 "AMDGPUISelDAGToDAG.cpp",
100 "AMDGPUISelLowering.cpp",
102 "AMDGPUInstrInfo.cpp",
103 "AMDGPUInstructionSelector.cpp",
104 "AMDGPULegalizerInfo.cpp",
105 "AMDGPULibCalls.cpp",
107 "AMDGPULowerIntrinsics.cpp",
108 "AMDGPULowerKernelArguments.cpp",
109 "AMDGPULowerKernelAttributes.cpp",
110 "AMDGPUMCInstLower.cpp",
111 "AMDGPUMachineCFGStructurizer.cpp",
112 "AMDGPUMachineFunction.cpp",
113 "AMDGPUMachineModuleInfo.cpp",
114 "AMDGPUMacroFusion.cpp",
115 "AMDGPUOpenCLEnqueuedBlockLowering.cpp",
116 "AMDGPUPerfHintAnalysis.cpp",
117 "AMDGPUPrintfRuntimeBinding.cpp",
118 "AMDGPUPromoteAlloca.cpp",
119 "AMDGPUPropagateAttributes.cpp",
120 "AMDGPURegisterBankInfo.cpp",
121 "AMDGPURegisterInfo.cpp",
122 "AMDGPURewriteOutArguments.cpp",
123 "AMDGPUSubtarget.cpp",
124 "AMDGPUTargetMachine.cpp",
125 "AMDGPUTargetObjectFile.cpp",
126 "AMDGPUTargetTransformInfo.cpp",
127 "AMDGPUUnifyDivergentExitNodes.cpp",
128 "AMDGPUUnifyMetadata.cpp",
129 "AMDILCFGStructurizer.cpp",
131 "GCNHazardRecognizer.cpp",
133 "GCNIterativeScheduler.cpp",
134 "GCNMinRegStrategy.cpp",
135 "GCNNSAReassign.cpp",
136 "GCNRegBankReassign.cpp",
137 "GCNRegPressure.cpp",
138 "GCNSchedStrategy.cpp",
139 "R600AsmPrinter.cpp",
140 "R600ClauseMergePass.cpp",
141 "R600ControlFlowFinalizer.cpp",
142 "R600EmitClauseMarkers.cpp",
143 "R600ExpandSpecialInstrs.cpp",
144 "R600FrameLowering.cpp",
145 "R600ISelLowering.cpp",
147 "R600MachineFunctionInfo.cpp",
148 "R600MachineScheduler.cpp",
149 "R600OpenCLImageTypeLoweringPass.cpp",
150 "R600OptimizeVectorRegisters.cpp",
151 "R600Packetizer.cpp",
152 "R600RegisterInfo.cpp",
154 "SIAnnotateControlFlow.cpp",
155 "SIFixSGPRCopies.cpp",
156 "SIFixVGPRCopies.cpp",
157 "SIFixupVectorISel.cpp",
158 "SIFoldOperands.cpp",
159 "SIFormMemoryClauses.cpp",
160 "SIFrameLowering.cpp",
161 "SIISelLowering.cpp",
163 "SIInsertWaitcnts.cpp",
165 "SILoadStoreOptimizer.cpp",
166 "SILowerControlFlow.cpp",
167 "SILowerI1Copies.cpp",
168 "SILowerSGPRSpills.cpp",
169 "SIMachineFunctionInfo.cpp",
170 "SIMachineScheduler.cpp",
171 "SIMemoryLegalizer.cpp",
172 "SIModeRegister.cpp",
173 "SIOptimizeExecMasking.cpp",
174 "SIOptimizeExecMaskingPreRA.cpp",
175 "SIPeepholeSDWA.cpp",
176 "SIPreAllocateWWMRegs.cpp",
177 "SIRegisterInfo.cpp",
178 "SIShrinkInstructions.cpp",
179 "SIWholeQuadMode.cpp",
183 # This is a bit different from most build files: Due to this group
184 # having the directory's name, "//llvm/lib/Target/AMDGPU" will refer to this
185 # target, which pulls in the code in this directory *and all subdirectories*.
186 # For most other directories, "//llvm/lib/Foo" only pulls in the code directly
187 # in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
188 # different behavior.
191 ":LLVMAMDGPUCodeGen",