1 import("//llvm/utils/TableGen/tablegen.gni")
3 # Generates ARMGenSystemRegister.inc
4 tablegen("ARMGenSystemRegister") {
5 visibility = [ ":Utils" ]
6 args = [ "-gen-searchable-tables" ]
10 static_library("Utils") {
11 output_name = "LLVMARMUtils"
13 ":ARMGenSystemRegister",
18 # MCTargetDesc depends on Utils, so we can't depend on the full
19 # MCTargetDesc target here: it would form a cycle.
20 "//llvm/lib/Target/ARM/MCTargetDesc:tablegen",
23 # ARMBaseInfo.h includes a header from MCTargetDesc,
24 # https://reviews.llvm.org/D35209#1075113 :-/
25 include_dirs = [ ".." ]