1 import("//llvm/utils/TableGen/tablegen.gni")
3 tablegen("PPCGenAsmWriter") {
4 visibility = [ ":MCTargetDesc" ]
5 args = [ "-gen-asm-writer" ]
9 tablegen("PPCGenInstrInfo") {
10 visibility = [ ":MCTargetDesc" ]
11 args = [ "-gen-instr-info" ]
15 tablegen("PPCGenMCCodeEmitter") {
16 visibility = [ ":MCTargetDesc" ]
17 args = [ "-gen-emitter" ]
21 tablegen("PPCGenRegisterInfo") {
22 visibility = [ ":MCTargetDesc" ]
23 args = [ "-gen-register-info" ]
27 tablegen("PPCGenSubtargetInfo") {
28 visibility = [ ":MCTargetDesc" ]
29 args = [ "-gen-subtarget" ]
33 static_library("MCTargetDesc") {
34 output_name = "LLVMPowerPCDesc"
36 # This should contain tablegen targets generating .inc files included
37 # by other targets. .inc files only used by .cpp files in this directory
38 # should be in deps instead.
41 ":PPCGenRegisterInfo",
42 ":PPCGenSubtargetInfo",
46 ":PPCGenMCCodeEmitter",
49 "//llvm/lib/Target/PowerPC/TargetInfo",
51 include_dirs = [ ".." ]
54 "PPCELFObjectWriter.cpp",
57 "PPCMCCodeEmitter.cpp",
59 "PPCMCTargetDesc.cpp",
60 "PPCMachObjectWriter.cpp",
62 "PPCXCOFFObjectWriter.cpp",