unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

   1 //===- KnownBitsTest.cpp -------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "GISelMITest.h"
  10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
  11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  12
  13 TEST_F(GISelMITest, TestKnownBitsCst) {
  14   StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 1\n"
  15                         "  %4:_(s8) = COPY %3\n";
  16   setUp(MIRString);
  17   if (!TM)
  18     return;
  19   unsigned CopyReg = Copies[Copies.size() - 1];
  20   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  21   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
  22   unsigned DstReg = FinalCopy->getOperand(0).getReg();
  23   GISelKnownBits Info(*MF);
  24   KnownBits Res = Info.getKnownBits(SrcReg);
  25   EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
  26   EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
  27
  28   KnownBits Res2 = Info.getKnownBits(DstReg);
  29   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
  30   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
  31 }
  32
  33 TEST_F(GISelMITest, TestKnownBitsCstWithClass) {
  34   StringRef MIRString = "  %10:gpr32 = MOVi32imm 1\n"
  35                         "  %4:_(s32) = COPY %10\n";
  36   setUp(MIRString);
  37   if (!TM)
  38     return;
  39   unsigned CopyReg = Copies[Copies.size() - 1];
  40   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  41   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
  42   unsigned DstReg = FinalCopy->getOperand(0).getReg();
  43   GISelKnownBits Info(*MF);
  44   KnownBits Res = Info.getKnownBits(SrcReg);
  45   // We can't analyze %3 due to the register class constraint. We will get a
  46   // default-constructed KnownBits back.
  47   EXPECT_EQ((uint64_t)1, Res.getBitWidth());
  48   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
  49   EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
  50
  51   KnownBits Res2 = Info.getKnownBits(DstReg);
  52   // We still don't know the values due to the register class constraint but %4
  53   // did reveal the size of %3.
  54   EXPECT_EQ((uint64_t)32, Res2.getBitWidth());
  55   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
  56   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
  57 }
  58
  59 TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) {
  60   StringRef MIRString = "  %3:_(s16) = G_CONSTANT i16 256\n"
  61                         "  %4:_(p0) = G_INTTOPTR %3\n"
  62                         "  %5:_(s32) = G_PTRTOINT %4\n"
  63                         "  %6:_(s32) = COPY %5\n";
  64   setUp(MIRString);
  65   if (!TM)
  66     return;
  67   unsigned CopyReg = Copies[Copies.size() - 1];
  68   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  69   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
  70   GISelKnownBits Info(*MF);
  71   KnownBits Res = Info.getKnownBits(SrcReg);
  72   EXPECT_EQ(256u, Res.One.getZExtValue());
  73   EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
  74 }
  75 TEST_F(GISelMITest, TestKnownBitsXOR) {
  76   StringRef MIRString = "  %3:_(s8) = G_CONSTANT i8 4\n"
  77                         "  %4:_(s8) = G_CONSTANT i8 7\n"
  78                         "  %5:_(s8) = G_XOR %3, %4\n"
  79                         "  %6:_(s8) = COPY %5\n";
  80   setUp(MIRString);
  81   if (!TM)
  82     return;
  83   unsigned CopyReg = Copies[Copies.size() - 1];
  84   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  85   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
  86   GISelKnownBits Info(*MF);
  87   KnownBits Res = Info.getKnownBits(SrcReg);
  88   EXPECT_EQ(3u, Res.One.getZExtValue());
  89   EXPECT_EQ(252u, Res.Zero.getZExtValue());
  90 }
  91
  92 TEST_F(GISelMITest, TestKnownBits) {
  93
  94   StringRef MIR = "  %3:_(s32) = G_TRUNC %0\n"
  95                   "  %4:_(s32) = G_TRUNC %1\n"
  96                   "  %5:_(s32) = G_CONSTANT i32 5\n"
  97                   "  %6:_(s32) = G_CONSTANT i32 24\n"
  98                   "  %7:_(s32) = G_CONSTANT i32 28\n"
  99                   "  %14:_(p0) = G_INTTOPTR %7\n"
 100                   "  %16:_(s32) = G_PTRTOINT %14\n"
 101                   "  %8:_(s32) = G_SHL %3, %5\n"
 102                   "  %9:_(s32) = G_SHL %4, %5\n"
 103                   "  %10:_(s32) = G_OR %8, %6\n"
 104                   "  %11:_(s32) = G_OR %9, %16\n"
 105                   "  %12:_(s32) = G_MUL %10, %11\n"
 106                   "  %13:_(s32) = COPY %12\n";
 107   setUp(MIR);
 108   if (!TM)
 109     return;
 110   unsigned CopyReg = Copies[Copies.size() - 1];
 111   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 112   unsigned SrcReg = FinalCopy->getOperand(1).getReg();
 113   GISelKnownBits Info(*MF);
 114   KnownBits Known = Info.getKnownBits(SrcReg);
 115   EXPECT_FALSE(Known.hasConflict());
 116   EXPECT_EQ(0u, Known.One.getZExtValue());
 117   EXPECT_EQ(31u, Known.Zero.getZExtValue());
 118   APInt Zeroes = Info.getKnownZeroes(SrcReg);
 119   EXPECT_EQ(Known.Zero, Zeroes);
 120 }
 121
 122 TEST_F(GISelMITest, TestSignBitIsZero) {
 123   if (!TM)
 124     return;
 125
 126   const LLT S32 = LLT::scalar(32);
 127   auto SignBit = B.buildConstant(S32, 0x8000000);
 128   auto Zero = B.buildConstant(S32, 0);
 129
 130   GISelKnownBits KnownBits(*MF);
 131
 132   EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
 133   EXPECT_FALSE(KnownBits.signBitIsZero(Zero.getReg(0)));
 134   EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
 135   EXPECT_TRUE(KnownBits.signBitIsZero(SignBit.getReg(0)));
 136 }