lib/Target/Hexagon/HexagonISelLowering.h

   1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
  15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
  16
  17 #include "Hexagon.h"
  18 #include "llvm/ADT/StringRef.h"
  19 #include "llvm/CodeGen/ISDOpcodes.h"
  20 #include "llvm/CodeGen/SelectionDAGNodes.h"
  21 #include "llvm/CodeGen/TargetLowering.h"
  22 #include "llvm/CodeGen/ValueTypes.h"
  23 #include "llvm/IR/CallingConv.h"
  24 #include "llvm/IR/InlineAsm.h"
  25 #include "llvm/Support/MachineValueType.h"
  26 #include <cstdint>
  27 #include <utility>
  28
  29 namespace llvm {
  30
  31 namespace HexagonISD {
  32
  33     enum NodeType : unsigned {
  34       OP_BEGIN = ISD::BUILTIN_OP_END,
  35
  36       CONST32 = OP_BEGIN,
  37       CONST32_GP,  // For marking data present in GP.
  38       ADDC,        // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
  39       SUBC,        // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
  40       ALLOCA,
  41
  42       AT_GOT,      // Index in GOT.
  43       AT_PCREL,    // Offset relative to PC.
  44
  45       CALL,        // Function call.
  46       CALLnr,      // Function call that does not return.
  47       CALLR,
  48
  49       RET_FLAG,    // Return with a flag operand.
  50       BARRIER,     // Memory barrier.
  51       JT,          // Jump table.
  52       CP,          // Constant pool.
  53
  54       COMBINE,
  55       VSPLAT,      // Generic splat, selection depends on argument/return
  56                    // types.
  57       VASL,
  58       VASR,
  59       VLSR,
  60
  61       TSTBIT,
  62       INSERT,
  63       EXTRACTU,
  64       VEXTRACTW,
  65       VINSERTW0,
  66       VROR,
  67       TC_RETURN,
  68       EH_RETURN,
  69       DCFETCH,
  70       READCYCLE,
  71       D2P,         // Convert 8-byte value to 8-bit predicate register. [*]
  72       P2D,         // Convert 8-bit predicate register to 8-byte value. [*]
  73       V2Q,         // Convert HVX vector to a vector predicate reg. [*]
  74       Q2V,         // Convert vector predicate to an HVX vector. [*]
  75                    // [*] The equivalence is defined as "Q <=> (V != 0)",
  76                    //     where the != operation compares bytes.
  77                    // Note: V != 0 is implemented as V >u 0.
  78       QCAT,
  79       QTRUE,
  80       QFALSE,
  81       VZERO,
  82       VSPLATW,     // HVX splat of a 32-bit word with an arbitrary result type.
  83       TYPECAST,    // No-op that's used to convert between different legal
  84                    // types in a register.
  85       VALIGN,      // Align two vectors (in Op0, Op1) to one that would have
  86                    // been loaded from address in Op2.
  87       VALIGNADDR,  // Align vector address: Op0 & -Op1, except when it is
  88                    // an address in a vector load, then it's a no-op.
  89       OP_END
  90     };
  91
  92 } // end namespace HexagonISD
  93
  94   class HexagonSubtarget;
  95
  96   class HexagonTargetLowering : public TargetLowering {
  97     int VarArgsFrameOffset;   // Frame offset to start of varargs area.
  98     const HexagonTargetMachine &HTM;
  99     const HexagonSubtarget &Subtarget;
 100
 101     bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
 102         const;
 103
 104   public:
 105     explicit HexagonTargetLowering(const TargetMachine &TM,
 106                                    const HexagonSubtarget &ST);
 107
 108     bool isHVXVectorType(MVT Ty) const;
 109
 110     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
 111     /// for tail call optimization. Targets which want to do tail call
 112     /// optimization should implement this function.
 113     bool IsEligibleForTailCallOptimization(SDValue Callee,
 114         CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
 115         bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
 116         const SmallVectorImpl<SDValue> &OutVals,
 117         const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
 118
 119     bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
 120                             MachineFunction &MF,
 121                             unsigned Intrinsic) const override;
 122
 123     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 124     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 125
 126     bool isCheapToSpeculateCttz() const override { return true; }
 127     bool isCheapToSpeculateCtlz() const override { return true; }
 128     bool isCtlzFast() const override { return true; }
 129
 130     bool hasBitTest(SDValue X, SDValue Y) const override;
 131
 132     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 133
 134     /// Return true if an FMA operation is faster than a pair of mul and add
 135     /// instructions. fmuladd intrinsics will be expanded to FMAs when this
 136     /// method returns true (and FMAs are legal), otherwise fmuladd is
 137     /// expanded to mul + add.
 138     bool isFMAFasterThanFMulAndFAdd(EVT) const override;
 139
 140     // Should we expand the build vector with shuffles?
 141     bool shouldExpandBuildVectorWithShuffles(EVT VT,
 142         unsigned DefinedValues) const override;
 143
 144     bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
 145     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
 146         const override;
 147
 148     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 149     void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
 150                                SelectionDAG &DAG) const override;
 151     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
 152                             SelectionDAG &DAG) const override;
 153
 154     const char *getTargetNodeName(unsigned Opcode) const override;
 155
 156     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 157     SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
 158     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 159     SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 160     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 161     SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
 162     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 163     SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
 164     SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
 165     SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
 166     SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 167     SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 168     SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 169     SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
 170     SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
 171     SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
 172     SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
 173     SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;
 174
 175     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 176     SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
 177     SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
 178     SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
 179     SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
 180     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
 181     SDValue
 182     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 183                          const SmallVectorImpl<ISD::InputArg> &Ins,
 184                          const SDLoc &dl, SelectionDAG &DAG,
 185                          SmallVectorImpl<SDValue> &InVals) const override;
 186     SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
 187     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 188     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 189     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
 190         SelectionDAG &DAG) const;
 191     SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
 192         SelectionDAG &DAG) const;
 193     SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
 194         SelectionDAG &DAG) const;
 195     SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
 196         GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
 197         unsigned ReturnReg, unsigned char OperandFlags) const;
 198     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
 199
 200     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 201         SmallVectorImpl<SDValue> &InVals) const override;
 202     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 203                             CallingConv::ID CallConv, bool isVarArg,
 204                             const SmallVectorImpl<ISD::InputArg> &Ins,
 205                             const SDLoc &dl, SelectionDAG &DAG,
 206                             SmallVectorImpl<SDValue> &InVals,
 207                             const SmallVectorImpl<SDValue> &OutVals,
 208                             SDValue Callee) const;
 209
 210     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 211     SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
 212     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 213     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
 214     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 215
 216     bool CanLowerReturn(CallingConv::ID CallConv,
 217                         MachineFunction &MF, bool isVarArg,
 218                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 219                         LLVMContext &Context) const override;
 220
 221     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 222                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 223                         const SmallVectorImpl<SDValue> &OutVals,
 224                         const SDLoc &dl, SelectionDAG &DAG) const override;
 225
 226     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 227
 228     unsigned getRegisterByName(const char* RegName, EVT VT,
 229                                SelectionDAG &DAG) const override;
 230
 231     /// If a physical register, this returns the register that receives the
 232     /// exception address on entry to an EH pad.
 233     unsigned
 234     getExceptionPointerRegister(const Constant *PersonalityFn) const override {
 235       return Hexagon::R0;
 236     }
 237
 238     /// If a physical register, this returns the register that receives the
 239     /// exception typeid on entry to a landing pad.
 240     unsigned
 241     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
 242       return Hexagon::R1;
 243     }
 244
 245     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 246     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 247     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 248
 249     EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
 250                            EVT VT) const override {
 251       if (!VT.isVector())
 252         return MVT::i1;
 253       else
 254         return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
 255     }
 256
 257     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
 258                                     SDValue &Base, SDValue &Offset,
 259                                     ISD::MemIndexedMode &AM,
 260                                     SelectionDAG &DAG) const override;
 261
 262     ConstraintType getConstraintType(StringRef Constraint) const override;
 263
 264     std::pair<unsigned, const TargetRegisterClass *>
 265     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 266                                  StringRef Constraint, MVT VT) const override;
 267
 268     unsigned
 269     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 270       if (ConstraintCode == "o")
 271         return InlineAsm::Constraint_o;
 272       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 273     }
 274
 275     // Intrinsics
 276     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 277     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
 278     /// isLegalAddressingMode - Return true if the addressing mode represented
 279     /// by AM is legal for this target, for a load/store of the specified type.
 280     /// The type may be VoidTy, in which case only return true if the addressing
 281     /// mode is legal for a load/store of any legal type.
 282     /// TODO: Handle pre/postinc as well.
 283     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 284                                Type *Ty, unsigned AS,
 285                                Instruction *I = nullptr) const override;
 286     /// Return true if folding a constant offset with the given GlobalAddress
 287     /// is legal.  It is frequently not legal in PIC relocation models.
 288     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 289
 290     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 291                       bool ForCodeSize) const override;
 292
 293     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 294     /// icmp immediate, that is the target has icmp instructions which can
 295     /// compare a register against the immediate without having to materialize
 296     /// the immediate into a register.
 297     bool isLegalICmpImmediate(int64_t Imm) const override;
 298
 299     EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
 300         unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
 301         const AttributeList &FuncAttributes) const override;
 302
 303     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
 304         unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override;
 305
 306     /// Returns relocation base for the given PIC jumptable.
 307     SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
 308                                      const override;
 309
 310     bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
 311                                EVT NewVT) const override;
 312
 313     // Handling of atomic RMW instructions.
 314     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
 315         AtomicOrdering Ord) const override;
 316     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
 317         Value *Addr, AtomicOrdering Ord) const override;
 318     AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
 319     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
 320     AtomicExpansionKind
 321     shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
 322
 323     AtomicExpansionKind
 324     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
 325       return AtomicExpansionKind::LLSC;
 326     }
 327
 328   private:
 329     void initializeHVXLowering();
 330     void validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
 331                                    unsigned NeedAlign) const;
 332
 333     std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
 334
 335     bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
 336                                  SelectionDAG &DAG,
 337                                  MutableArrayRef<ConstantInt*> Consts) const;
 338     SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
 339                           SelectionDAG &DAG) const;
 340     SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
 341                           SelectionDAG &DAG) const;
 342     SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
 343                           MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
 344     SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
 345                          const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
 346     SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
 347                             SelectionDAG &DAG) const;
 348     SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
 349                               SelectionDAG &DAG) const;
 350     SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
 351
 352     bool isUndef(SDValue Op) const {
 353       if (Op.isMachineOpcode())
 354         return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
 355       return Op.getOpcode() == ISD::UNDEF;
 356     }
 357     SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
 358                      ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
 359       SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
 360       return SDValue(N, 0);
 361     }
 362     SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
 363
 364     using VectorPair = std::pair<SDValue, SDValue>;
 365     using TypePair = std::pair<MVT, MVT>;
 366
 367     SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
 368                    const SDLoc &dl, SelectionDAG &DAG) const;
 369
 370     MVT ty(SDValue Op) const {
 371       return Op.getValueType().getSimpleVT();
 372     }
 373     TypePair ty(const VectorPair &Ops) const {
 374       return { Ops.first.getValueType().getSimpleVT(),
 375                Ops.second.getValueType().getSimpleVT() };
 376     }
 377     MVT tyScalar(MVT Ty) const {
 378       if (!Ty.isVector())
 379         return Ty;
 380       return MVT::getIntegerVT(Ty.getSizeInBits());
 381     }
 382     MVT tyVector(MVT Ty, MVT ElemTy) const {
 383       if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
 384         return Ty;
 385       unsigned TyWidth = Ty.getSizeInBits();
 386       unsigned ElemWidth = ElemTy.getSizeInBits();
 387       assert((TyWidth % ElemWidth) == 0);
 388       return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
 389     }
 390
 391     MVT typeJoin(const TypePair &Tys) const;
 392     TypePair typeSplit(MVT Ty) const;
 393     MVT typeExtElem(MVT VecTy, unsigned Factor) const;
 394     MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
 395
 396     SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
 397                    SelectionDAG &DAG) const;
 398     VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
 399     SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
 400
 401     bool isHvxSingleTy(MVT Ty) const;
 402     bool isHvxPairTy(MVT Ty) const;
 403     SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
 404                                SelectionDAG &DAG) const;
 405     SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
 406     SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
 407                            ArrayRef<int> Mask, SelectionDAG &DAG) const;
 408
 409     SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
 410                               MVT VecTy, SelectionDAG &DAG) const;
 411     SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
 412                                MVT VecTy, SelectionDAG &DAG) const;
 413     SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
 414                                 unsigned BitBytes, bool ZeroFill,
 415                                 SelectionDAG &DAG) const;
 416     SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
 417                                  MVT ResTy, SelectionDAG &DAG) const;
 418     SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
 419                                   MVT ResTy, SelectionDAG &DAG) const;
 420     SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
 421                                 const SDLoc &dl, SelectionDAG &DAG) const;
 422     SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
 423                                  const SDLoc &dl, SelectionDAG &DAG) const;
 424     SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
 425                                    MVT ResTy, SelectionDAG &DAG) const;
 426     SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
 427                                     MVT ResTy, SelectionDAG &DAG) const;
 428     SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
 429                                   const SDLoc &dl, SelectionDAG &DAG) const;
 430     SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
 431                                    const SDLoc &dl, SelectionDAG &DAG) const;
 432     SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
 433                                 bool ZeroExt, SelectionDAG &DAG) const;
 434
 435     SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
 436     SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
 437     SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
 438     SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
 439     SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
 440     SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
 441
 442     SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
 443     SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
 444     SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
 445     SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
 446     SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
 447     SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
 448     SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
 449     SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
 450     SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
 451
 452     SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
 453     SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
 454
 455     std::pair<const TargetRegisterClass*, uint8_t>
 456     findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
 457         const override;
 458
 459     bool isHvxOperation(SDValue Op) const;
 460     SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
 461   };
 462
 463 } // end namespace llvm
 464
 465 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H