lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

   1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file provides WebAssembly-specific target descriptions.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
  16
  17 #include "../WebAssemblySubtarget.h"
  18 #include "llvm/BinaryFormat/Wasm.h"
  19 #include "llvm/MC/MCInstrDesc.h"
  20 #include "llvm/Support/DataTypes.h"
  21 #include <memory>
  22
  23 namespace llvm {
  24
  25 class MCAsmBackend;
  26 class MCCodeEmitter;
  27 class MCContext;
  28 class MCInstrInfo;
  29 class MCObjectTargetWriter;
  30 class MCSubtargetInfo;
  31 class MVT;
  32 class Target;
  33 class Triple;
  34 class raw_pwrite_stream;
  35
  36 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
  37
  38 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
  39
  40 std::unique_ptr<MCObjectTargetWriter>
  41 createWebAssemblyWasmObjectWriter(bool Is64Bit);
  42
  43 namespace WebAssembly {
  44 enum OperandType {
  45   /// Basic block label in a branch construct.
  46   OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
  47   /// Local index.
  48   OPERAND_LOCAL,
  49   /// Global index.
  50   OPERAND_GLOBAL,
  51   /// 32-bit integer immediates.
  52   OPERAND_I32IMM,
  53   /// 64-bit integer immediates.
  54   OPERAND_I64IMM,
  55   /// 32-bit floating-point immediates.
  56   OPERAND_F32IMM,
  57   /// 64-bit floating-point immediates.
  58   OPERAND_F64IMM,
  59   /// 8-bit vector lane immediate
  60   OPERAND_VEC_I8IMM,
  61   /// 16-bit vector lane immediate
  62   OPERAND_VEC_I16IMM,
  63   /// 32-bit vector lane immediate
  64   OPERAND_VEC_I32IMM,
  65   /// 64-bit vector lane immediate
  66   OPERAND_VEC_I64IMM,
  67   /// 32-bit unsigned function indices.
  68   OPERAND_FUNCTION32,
  69   /// 32-bit unsigned memory offsets.
  70   OPERAND_OFFSET32,
  71   /// p2align immediate for load and store address alignment.
  72   OPERAND_P2ALIGN,
  73   /// signature immediate for block/loop.
  74   OPERAND_SIGNATURE,
  75   /// type signature immediate for call_indirect.
  76   OPERAND_TYPEINDEX,
  77   /// Event index.
  78   OPERAND_EVENT,
  79   /// A list of branch targets for br_list.
  80   OPERAND_BRLIST,
  81 };
  82 } // end namespace WebAssembly
  83
  84 namespace WebAssemblyII {
  85
  86 /// Target Operand Flag enum.
  87 enum TOF {
  88   MO_NO_FLAG = 0,
  89
  90   // On a symbol operand this indicates that the immediate is a wasm global
  91   // index.  The value of the wasm global will be set to the symbol address at
  92   // runtime.  This adds a level of indirection similar to the GOT on native
  93   // platforms.
  94   MO_GOT,
  95
  96   // On a symbol operand this indicates that the immediate is the symbol
  97   // address relative the __memory_base wasm global.
  98   // Only applicable to data symbols.
  99   MO_MEMORY_BASE_REL,
 100
 101   // On a symbol operand this indicates that the immediate is the symbol
 102   // address relative the __table_base wasm global.
 103   // Only applicable to function symbols.
 104   MO_TABLE_BASE_REL,
 105 };
 106
 107 } // end namespace WebAssemblyII
 108
 109 } // end namespace llvm
 110
 111 // Defines symbolic names for WebAssembly registers. This defines a mapping from
 112 // register name to register number.
 113 //
 114 #define GET_REGINFO_ENUM
 115 #include "WebAssemblyGenRegisterInfo.inc"
 116
 117 // Defines symbolic names for the WebAssembly instructions.
 118 //
 119 #define GET_INSTRINFO_ENUM
 120 #include "WebAssemblyGenInstrInfo.inc"
 121
 122 namespace llvm {
 123 namespace WebAssembly {
 124
 125 /// This is used to indicate block signatures.
 126 enum class ExprType : unsigned {
 127   Void = 0x40,
 128   I32 = 0x7F,
 129   I64 = 0x7E,
 130   F32 = 0x7D,
 131   F64 = 0x7C,
 132   V128 = 0x7B,
 133   Exnref = 0x68,
 134   Invalid = 0x00
 135 };
 136
 137 /// Instruction opcodes emitted via means other than CodeGen.
 138 static const unsigned Nop = 0x01;
 139 static const unsigned End = 0x0b;
 140
 141 wasm::ValType toValType(const MVT &Ty);
 142
 143 /// Return the default p2align value for a load or store with the given opcode.
 144 inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
 145   switch (Opc) {
 146   case WebAssembly::LOAD8_S_I32:
 147   case WebAssembly::LOAD8_S_I32_S:
 148   case WebAssembly::LOAD8_U_I32:
 149   case WebAssembly::LOAD8_U_I32_S:
 150   case WebAssembly::LOAD8_S_I64:
 151   case WebAssembly::LOAD8_S_I64_S:
 152   case WebAssembly::LOAD8_U_I64:
 153   case WebAssembly::LOAD8_U_I64_S:
 154   case WebAssembly::ATOMIC_LOAD8_U_I32:
 155   case WebAssembly::ATOMIC_LOAD8_U_I32_S:
 156   case WebAssembly::ATOMIC_LOAD8_U_I64:
 157   case WebAssembly::ATOMIC_LOAD8_U_I64_S:
 158   case WebAssembly::STORE8_I32:
 159   case WebAssembly::STORE8_I32_S:
 160   case WebAssembly::STORE8_I64:
 161   case WebAssembly::STORE8_I64_S:
 162   case WebAssembly::ATOMIC_STORE8_I32:
 163   case WebAssembly::ATOMIC_STORE8_I32_S:
 164   case WebAssembly::ATOMIC_STORE8_I64:
 165   case WebAssembly::ATOMIC_STORE8_I64_S:
 166   case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
 167   case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
 168   case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
 169   case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
 170   case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
 171   case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
 172   case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
 173   case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
 174   case WebAssembly::ATOMIC_RMW8_U_AND_I32:
 175   case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
 176   case WebAssembly::ATOMIC_RMW8_U_AND_I64:
 177   case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
 178   case WebAssembly::ATOMIC_RMW8_U_OR_I32:
 179   case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
 180   case WebAssembly::ATOMIC_RMW8_U_OR_I64:
 181   case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
 182   case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
 183   case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
 184   case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
 185   case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
 186   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
 187   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
 188   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
 189   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
 190   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
 191   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
 192   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
 193   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
 194     return 0;
 195   case WebAssembly::LOAD16_S_I32:
 196   case WebAssembly::LOAD16_S_I32_S:
 197   case WebAssembly::LOAD16_U_I32:
 198   case WebAssembly::LOAD16_U_I32_S:
 199   case WebAssembly::LOAD16_S_I64:
 200   case WebAssembly::LOAD16_S_I64_S:
 201   case WebAssembly::LOAD16_U_I64:
 202   case WebAssembly::LOAD16_U_I64_S:
 203   case WebAssembly::ATOMIC_LOAD16_U_I32:
 204   case WebAssembly::ATOMIC_LOAD16_U_I32_S:
 205   case WebAssembly::ATOMIC_LOAD16_U_I64:
 206   case WebAssembly::ATOMIC_LOAD16_U_I64_S:
 207   case WebAssembly::STORE16_I32:
 208   case WebAssembly::STORE16_I32_S:
 209   case WebAssembly::STORE16_I64:
 210   case WebAssembly::STORE16_I64_S:
 211   case WebAssembly::ATOMIC_STORE16_I32:
 212   case WebAssembly::ATOMIC_STORE16_I32_S:
 213   case WebAssembly::ATOMIC_STORE16_I64:
 214   case WebAssembly::ATOMIC_STORE16_I64_S:
 215   case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
 216   case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
 217   case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
 218   case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
 219   case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
 220   case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
 221   case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
 222   case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
 223   case WebAssembly::ATOMIC_RMW16_U_AND_I32:
 224   case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
 225   case WebAssembly::ATOMIC_RMW16_U_AND_I64:
 226   case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
 227   case WebAssembly::ATOMIC_RMW16_U_OR_I32:
 228   case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
 229   case WebAssembly::ATOMIC_RMW16_U_OR_I64:
 230   case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
 231   case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
 232   case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
 233   case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
 234   case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
 235   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
 236   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
 237   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
 238   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
 239   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
 240   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
 241   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
 242   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
 243     return 1;
 244   case WebAssembly::LOAD_I32:
 245   case WebAssembly::LOAD_I32_S:
 246   case WebAssembly::LOAD_F32:
 247   case WebAssembly::LOAD_F32_S:
 248   case WebAssembly::STORE_I32:
 249   case WebAssembly::STORE_I32_S:
 250   case WebAssembly::STORE_F32:
 251   case WebAssembly::STORE_F32_S:
 252   case WebAssembly::LOAD32_S_I64:
 253   case WebAssembly::LOAD32_S_I64_S:
 254   case WebAssembly::LOAD32_U_I64:
 255   case WebAssembly::LOAD32_U_I64_S:
 256   case WebAssembly::STORE32_I64:
 257   case WebAssembly::STORE32_I64_S:
 258   case WebAssembly::ATOMIC_LOAD_I32:
 259   case WebAssembly::ATOMIC_LOAD_I32_S:
 260   case WebAssembly::ATOMIC_LOAD32_U_I64:
 261   case WebAssembly::ATOMIC_LOAD32_U_I64_S:
 262   case WebAssembly::ATOMIC_STORE_I32:
 263   case WebAssembly::ATOMIC_STORE_I32_S:
 264   case WebAssembly::ATOMIC_STORE32_I64:
 265   case WebAssembly::ATOMIC_STORE32_I64_S:
 266   case WebAssembly::ATOMIC_RMW_ADD_I32:
 267   case WebAssembly::ATOMIC_RMW_ADD_I32_S:
 268   case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
 269   case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
 270   case WebAssembly::ATOMIC_RMW_SUB_I32:
 271   case WebAssembly::ATOMIC_RMW_SUB_I32_S:
 272   case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
 273   case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
 274   case WebAssembly::ATOMIC_RMW_AND_I32:
 275   case WebAssembly::ATOMIC_RMW_AND_I32_S:
 276   case WebAssembly::ATOMIC_RMW32_U_AND_I64:
 277   case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
 278   case WebAssembly::ATOMIC_RMW_OR_I32:
 279   case WebAssembly::ATOMIC_RMW_OR_I32_S:
 280   case WebAssembly::ATOMIC_RMW32_U_OR_I64:
 281   case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
 282   case WebAssembly::ATOMIC_RMW_XOR_I32:
 283   case WebAssembly::ATOMIC_RMW_XOR_I32_S:
 284   case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
 285   case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
 286   case WebAssembly::ATOMIC_RMW_XCHG_I32:
 287   case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
 288   case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
 289   case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
 290   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
 291   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
 292   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
 293   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
 294   case WebAssembly::ATOMIC_NOTIFY:
 295   case WebAssembly::ATOMIC_NOTIFY_S:
 296   case WebAssembly::ATOMIC_WAIT_I32:
 297   case WebAssembly::ATOMIC_WAIT_I32_S:
 298     return 2;
 299   case WebAssembly::LOAD_I64:
 300   case WebAssembly::LOAD_I64_S:
 301   case WebAssembly::LOAD_F64:
 302   case WebAssembly::LOAD_F64_S:
 303   case WebAssembly::STORE_I64:
 304   case WebAssembly::STORE_I64_S:
 305   case WebAssembly::STORE_F64:
 306   case WebAssembly::STORE_F64_S:
 307   case WebAssembly::ATOMIC_LOAD_I64:
 308   case WebAssembly::ATOMIC_LOAD_I64_S:
 309   case WebAssembly::ATOMIC_STORE_I64:
 310   case WebAssembly::ATOMIC_STORE_I64_S:
 311   case WebAssembly::ATOMIC_RMW_ADD_I64:
 312   case WebAssembly::ATOMIC_RMW_ADD_I64_S:
 313   case WebAssembly::ATOMIC_RMW_SUB_I64:
 314   case WebAssembly::ATOMIC_RMW_SUB_I64_S:
 315   case WebAssembly::ATOMIC_RMW_AND_I64:
 316   case WebAssembly::ATOMIC_RMW_AND_I64_S:
 317   case WebAssembly::ATOMIC_RMW_OR_I64:
 318   case WebAssembly::ATOMIC_RMW_OR_I64_S:
 319   case WebAssembly::ATOMIC_RMW_XOR_I64:
 320   case WebAssembly::ATOMIC_RMW_XOR_I64_S:
 321   case WebAssembly::ATOMIC_RMW_XCHG_I64:
 322   case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
 323   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
 324   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
 325   case WebAssembly::ATOMIC_WAIT_I64:
 326   case WebAssembly::ATOMIC_WAIT_I64_S:
 327     return 3;
 328   case WebAssembly::LOAD_v16i8:
 329   case WebAssembly::LOAD_v16i8_S:
 330   case WebAssembly::LOAD_v8i16:
 331   case WebAssembly::LOAD_v8i16_S:
 332   case WebAssembly::LOAD_v4i32:
 333   case WebAssembly::LOAD_v4i32_S:
 334   case WebAssembly::LOAD_v2i64:
 335   case WebAssembly::LOAD_v2i64_S:
 336   case WebAssembly::LOAD_v4f32:
 337   case WebAssembly::LOAD_v4f32_S:
 338   case WebAssembly::LOAD_v2f64:
 339   case WebAssembly::LOAD_v2f64_S:
 340   case WebAssembly::STORE_v16i8:
 341   case WebAssembly::STORE_v16i8_S:
 342   case WebAssembly::STORE_v8i16:
 343   case WebAssembly::STORE_v8i16_S:
 344   case WebAssembly::STORE_v4i32:
 345   case WebAssembly::STORE_v4i32_S:
 346   case WebAssembly::STORE_v2i64:
 347   case WebAssembly::STORE_v2i64_S:
 348   case WebAssembly::STORE_v4f32:
 349   case WebAssembly::STORE_v4f32_S:
 350   case WebAssembly::STORE_v2f64:
 351   case WebAssembly::STORE_v2f64_S:
 352     return 4;
 353   default:
 354     return -1;
 355   }
 356 }
 357
 358 inline unsigned GetDefaultP2Align(unsigned Opc) {
 359   auto Align = GetDefaultP2AlignAny(Opc);
 360   if (Align == -1U) {
 361     llvm_unreachable("Only loads and stores have p2align values");
 362   }
 363   return Align;
 364 }
 365
 366 inline bool isArgument(unsigned Opc) {
 367   switch (Opc) {
 368   case WebAssembly::ARGUMENT_i32:
 369   case WebAssembly::ARGUMENT_i32_S:
 370   case WebAssembly::ARGUMENT_i64:
 371   case WebAssembly::ARGUMENT_i64_S:
 372   case WebAssembly::ARGUMENT_f32:
 373   case WebAssembly::ARGUMENT_f32_S:
 374   case WebAssembly::ARGUMENT_f64:
 375   case WebAssembly::ARGUMENT_f64_S:
 376   case WebAssembly::ARGUMENT_v16i8:
 377   case WebAssembly::ARGUMENT_v16i8_S:
 378   case WebAssembly::ARGUMENT_v8i16:
 379   case WebAssembly::ARGUMENT_v8i16_S:
 380   case WebAssembly::ARGUMENT_v4i32:
 381   case WebAssembly::ARGUMENT_v4i32_S:
 382   case WebAssembly::ARGUMENT_v2i64:
 383   case WebAssembly::ARGUMENT_v2i64_S:
 384   case WebAssembly::ARGUMENT_v4f32:
 385   case WebAssembly::ARGUMENT_v4f32_S:
 386   case WebAssembly::ARGUMENT_v2f64:
 387   case WebAssembly::ARGUMENT_v2f64_S:
 388   case WebAssembly::ARGUMENT_exnref:
 389   case WebAssembly::ARGUMENT_exnref_S:
 390     return true;
 391   default:
 392     return false;
 393   }
 394 }
 395
 396 inline bool isCopy(unsigned Opc) {
 397   switch (Opc) {
 398   case WebAssembly::COPY_I32:
 399   case WebAssembly::COPY_I32_S:
 400   case WebAssembly::COPY_I64:
 401   case WebAssembly::COPY_I64_S:
 402   case WebAssembly::COPY_F32:
 403   case WebAssembly::COPY_F32_S:
 404   case WebAssembly::COPY_F64:
 405   case WebAssembly::COPY_F64_S:
 406   case WebAssembly::COPY_V128:
 407   case WebAssembly::COPY_V128_S:
 408   case WebAssembly::COPY_EXNREF:
 409   case WebAssembly::COPY_EXNREF_S:
 410     return true;
 411   default:
 412     return false;
 413   }
 414 }
 415
 416 inline bool isTee(unsigned Opc) {
 417   switch (Opc) {
 418   case WebAssembly::TEE_I32:
 419   case WebAssembly::TEE_I32_S:
 420   case WebAssembly::TEE_I64:
 421   case WebAssembly::TEE_I64_S:
 422   case WebAssembly::TEE_F32:
 423   case WebAssembly::TEE_F32_S:
 424   case WebAssembly::TEE_F64:
 425   case WebAssembly::TEE_F64_S:
 426   case WebAssembly::TEE_V128:
 427   case WebAssembly::TEE_V128_S:
 428   case WebAssembly::TEE_EXNREF:
 429   case WebAssembly::TEE_EXNREF_S:
 430     return true;
 431   default:
 432     return false;
 433   }
 434 }
 435
 436 inline bool isCallDirect(unsigned Opc) {
 437   switch (Opc) {
 438   case WebAssembly::CALL_VOID:
 439   case WebAssembly::CALL_VOID_S:
 440   case WebAssembly::CALL_i32:
 441   case WebAssembly::CALL_i32_S:
 442   case WebAssembly::CALL_i64:
 443   case WebAssembly::CALL_i64_S:
 444   case WebAssembly::CALL_f32:
 445   case WebAssembly::CALL_f32_S:
 446   case WebAssembly::CALL_f64:
 447   case WebAssembly::CALL_f64_S:
 448   case WebAssembly::CALL_v16i8:
 449   case WebAssembly::CALL_v16i8_S:
 450   case WebAssembly::CALL_v8i16:
 451   case WebAssembly::CALL_v8i16_S:
 452   case WebAssembly::CALL_v4i32:
 453   case WebAssembly::CALL_v4i32_S:
 454   case WebAssembly::CALL_v2i64:
 455   case WebAssembly::CALL_v2i64_S:
 456   case WebAssembly::CALL_v4f32:
 457   case WebAssembly::CALL_v4f32_S:
 458   case WebAssembly::CALL_v2f64:
 459   case WebAssembly::CALL_v2f64_S:
 460   case WebAssembly::CALL_exnref:
 461   case WebAssembly::CALL_exnref_S:
 462   case WebAssembly::RET_CALL:
 463   case WebAssembly::RET_CALL_S:
 464     return true;
 465   default:
 466     return false;
 467   }
 468 }
 469
 470 inline bool isCallIndirect(unsigned Opc) {
 471   switch (Opc) {
 472   case WebAssembly::CALL_INDIRECT_VOID:
 473   case WebAssembly::CALL_INDIRECT_VOID_S:
 474   case WebAssembly::CALL_INDIRECT_i32:
 475   case WebAssembly::CALL_INDIRECT_i32_S:
 476   case WebAssembly::CALL_INDIRECT_i64:
 477   case WebAssembly::CALL_INDIRECT_i64_S:
 478   case WebAssembly::CALL_INDIRECT_f32:
 479   case WebAssembly::CALL_INDIRECT_f32_S:
 480   case WebAssembly::CALL_INDIRECT_f64:
 481   case WebAssembly::CALL_INDIRECT_f64_S:
 482   case WebAssembly::CALL_INDIRECT_v16i8:
 483   case WebAssembly::CALL_INDIRECT_v16i8_S:
 484   case WebAssembly::CALL_INDIRECT_v8i16:
 485   case WebAssembly::CALL_INDIRECT_v8i16_S:
 486   case WebAssembly::CALL_INDIRECT_v4i32:
 487   case WebAssembly::CALL_INDIRECT_v4i32_S:
 488   case WebAssembly::CALL_INDIRECT_v2i64:
 489   case WebAssembly::CALL_INDIRECT_v2i64_S:
 490   case WebAssembly::CALL_INDIRECT_v4f32:
 491   case WebAssembly::CALL_INDIRECT_v4f32_S:
 492   case WebAssembly::CALL_INDIRECT_v2f64:
 493   case WebAssembly::CALL_INDIRECT_v2f64_S:
 494   case WebAssembly::CALL_INDIRECT_exnref:
 495   case WebAssembly::CALL_INDIRECT_exnref_S:
 496   case WebAssembly::RET_CALL_INDIRECT:
 497   case WebAssembly::RET_CALL_INDIRECT_S:
 498     return true;
 499   default:
 500     return false;
 501   }
 502 }
 503
 504 /// Returns the operand number of a callee, assuming the argument is a call
 505 /// instruction.
 506 inline unsigned getCalleeOpNo(unsigned Opc) {
 507   switch (Opc) {
 508   case WebAssembly::CALL_VOID:
 509   case WebAssembly::CALL_VOID_S:
 510   case WebAssembly::CALL_INDIRECT_VOID:
 511   case WebAssembly::CALL_INDIRECT_VOID_S:
 512   case WebAssembly::RET_CALL:
 513   case WebAssembly::RET_CALL_S:
 514   case WebAssembly::RET_CALL_INDIRECT:
 515   case WebAssembly::RET_CALL_INDIRECT_S:
 516     return 0;
 517   case WebAssembly::CALL_i32:
 518   case WebAssembly::CALL_i32_S:
 519   case WebAssembly::CALL_i64:
 520   case WebAssembly::CALL_i64_S:
 521   case WebAssembly::CALL_f32:
 522   case WebAssembly::CALL_f32_S:
 523   case WebAssembly::CALL_f64:
 524   case WebAssembly::CALL_f64_S:
 525   case WebAssembly::CALL_v16i8:
 526   case WebAssembly::CALL_v16i8_S:
 527   case WebAssembly::CALL_v8i16:
 528   case WebAssembly::CALL_v8i16_S:
 529   case WebAssembly::CALL_v4i32:
 530   case WebAssembly::CALL_v4i32_S:
 531   case WebAssembly::CALL_v2i64:
 532   case WebAssembly::CALL_v2i64_S:
 533   case WebAssembly::CALL_v4f32:
 534   case WebAssembly::CALL_v4f32_S:
 535   case WebAssembly::CALL_v2f64:
 536   case WebAssembly::CALL_v2f64_S:
 537   case WebAssembly::CALL_exnref:
 538   case WebAssembly::CALL_exnref_S:
 539   case WebAssembly::CALL_INDIRECT_i32:
 540   case WebAssembly::CALL_INDIRECT_i32_S:
 541   case WebAssembly::CALL_INDIRECT_i64:
 542   case WebAssembly::CALL_INDIRECT_i64_S:
 543   case WebAssembly::CALL_INDIRECT_f32:
 544   case WebAssembly::CALL_INDIRECT_f32_S:
 545   case WebAssembly::CALL_INDIRECT_f64:
 546   case WebAssembly::CALL_INDIRECT_f64_S:
 547   case WebAssembly::CALL_INDIRECT_v16i8:
 548   case WebAssembly::CALL_INDIRECT_v16i8_S:
 549   case WebAssembly::CALL_INDIRECT_v8i16:
 550   case WebAssembly::CALL_INDIRECT_v8i16_S:
 551   case WebAssembly::CALL_INDIRECT_v4i32:
 552   case WebAssembly::CALL_INDIRECT_v4i32_S:
 553   case WebAssembly::CALL_INDIRECT_v2i64:
 554   case WebAssembly::CALL_INDIRECT_v2i64_S:
 555   case WebAssembly::CALL_INDIRECT_v4f32:
 556   case WebAssembly::CALL_INDIRECT_v4f32_S:
 557   case WebAssembly::CALL_INDIRECT_v2f64:
 558   case WebAssembly::CALL_INDIRECT_v2f64_S:
 559   case WebAssembly::CALL_INDIRECT_exnref:
 560   case WebAssembly::CALL_INDIRECT_exnref_S:
 561     return 1;
 562   default:
 563     llvm_unreachable("Not a call instruction");
 564   }
 565 }
 566
 567 inline bool isMarker(unsigned Opc) {
 568   switch (Opc) {
 569   case WebAssembly::BLOCK:
 570   case WebAssembly::BLOCK_S:
 571   case WebAssembly::END_BLOCK:
 572   case WebAssembly::END_BLOCK_S:
 573   case WebAssembly::LOOP:
 574   case WebAssembly::LOOP_S:
 575   case WebAssembly::END_LOOP:
 576   case WebAssembly::END_LOOP_S:
 577   case WebAssembly::TRY:
 578   case WebAssembly::TRY_S:
 579   case WebAssembly::END_TRY:
 580   case WebAssembly::END_TRY_S:
 581     return true;
 582   default:
 583     return false;
 584   }
 585 }
 586
 587 } // end namespace WebAssembly
 588 } // end namespace llvm
 589
 590 #endif