lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer  -------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 ///
  11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  12 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  13 /// an MCObjectStreamer it outputs binary code.
  14 //
  15 //===----------------------------------------------------------------------===//
  16 //
  17
  18 #include "AMDGPUAsmPrinter.h"
  19 #include "AMDGPU.h"
  20 #include "AMDGPUSubtarget.h"
  21 #include "AMDGPUTargetMachine.h"
  22 #include "MCTargetDesc/AMDGPUInstPrinter.h"
  23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
  25 #include "R600AsmPrinter.h"
  26 #include "R600Defines.h"
  27 #include "R600MachineFunctionInfo.h"
  28 #include "R600RegisterInfo.h"
  29 #include "SIDefines.h"
  30 #include "SIInstrInfo.h"
  31 #include "SIMachineFunctionInfo.h"
  32 #include "SIRegisterInfo.h"
  33 #include "TargetInfo/AMDGPUTargetInfo.h"
  34 #include "Utils/AMDGPUBaseInfo.h"
  35 #include "llvm/BinaryFormat/ELF.h"
  36 #include "llvm/CodeGen/MachineFrameInfo.h"
  37 #include "llvm/IR/DiagnosticInfo.h"
  38 #include "llvm/MC/MCAssembler.h"
  39 #include "llvm/MC/MCContext.h"
  40 #include "llvm/MC/MCSectionELF.h"
  41 #include "llvm/MC/MCStreamer.h"
  42 #include "llvm/Support/AMDGPUMetadata.h"
  43 #include "llvm/Support/MathExtras.h"
  44 #include "llvm/Support/TargetParser.h"
  45 #include "llvm/Support/TargetRegistry.h"
  46 #include "llvm/Target/TargetLoweringObjectFile.h"
  47
  48 using namespace llvm;
  49 using namespace llvm::AMDGPU;
  50 using namespace llvm::AMDGPU::HSAMD;
  51
  52 // TODO: This should get the default rounding mode from the kernel. We just set
  53 // the default here, but this could change if the OpenCL rounding mode pragmas
  54 // are used.
  55 //
  56 // The denormal mode here should match what is reported by the OpenCL runtime
  57 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
  58 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
  59 //
  60 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
  61 // precision, and leaves single precision to flush all and does not report
  62 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
  63 // CL_FP_DENORM for both.
  64 //
  65 // FIXME: It seems some instructions do not support single precision denormals
  66 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
  67 // and sin_f32, cos_f32 on most parts).
  68
  69 // We want to use these instructions, and using fp32 denormals also causes
  70 // instructions to run at the double precision rate for the device so it's
  71 // probably best to just report no single precision denormals.
  72 static uint32_t getFPMode(const MachineFunction &F) {
  73   const GCNSubtarget& ST = F.getSubtarget<GCNSubtarget>();
  74   // TODO: Is there any real use for the flush in only / flush out only modes?
  75
  76   uint32_t FP32Denormals =
  77     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  78
  79   uint32_t FP64Denormals =
  80     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
  81
  82   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
  83          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
  84          FP_DENORM_MODE_SP(FP32Denormals) |
  85          FP_DENORM_MODE_DP(FP64Denormals);
  86 }
  87
  88 static AsmPrinter *
  89 createAMDGPUAsmPrinterPass(TargetMachine &tm,
  90                            std::unique_ptr<MCStreamer> &&Streamer) {
  91   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
  92 }
  93
  94 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
  95   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
  96                                      llvm::createR600AsmPrinterPass);
  97   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
  98                                      createAMDGPUAsmPrinterPass);
  99 }
 100
 101 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
 102                                    std::unique_ptr<MCStreamer> Streamer)
 103   : AsmPrinter(TM, std::move(Streamer)) {
 104     if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
 105       HSAMetadataStream.reset(new MetadataStreamerV3());
 106     else
 107       HSAMetadataStream.reset(new MetadataStreamerV2());
 108 }
 109
 110 StringRef AMDGPUAsmPrinter::getPassName() const {
 111   return "AMDGPU Assembly Printer";
 112 }
 113
 114 const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
 115   return TM.getMCSubtargetInfo();
 116 }
 117
 118 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
 119   if (!OutStreamer)
 120     return nullptr;
 121   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
 122 }
 123
 124 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
 125   if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
 126     std::string ExpectedTarget;
 127     raw_string_ostream ExpectedTargetOS(ExpectedTarget);
 128     IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
 129
 130     getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
 131   }
 132
 133   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
 134       TM.getTargetTriple().getOS() != Triple::AMDPAL)
 135     return;
 136
 137   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
 138     HSAMetadataStream->begin(M);
 139
 140   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
 141     getTargetStreamer()->getPALMetadata()->readFromIR(M);
 142
 143   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
 144     return;
 145
 146   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
 147   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
 148     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
 149
 150   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
 151   IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
 152   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
 153       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
 154 }
 155
 156 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
 157   // Following code requires TargetStreamer to be present.
 158   if (!getTargetStreamer())
 159     return;
 160
 161   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
 162     // Emit ISA Version (NT_AMD_AMDGPU_ISA).
 163     std::string ISAVersionString;
 164     raw_string_ostream ISAVersionStream(ISAVersionString);
 165     IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
 166     getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
 167   }
 168
 169   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
 170   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
 171     HSAMetadataStream->end();
 172     bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
 173     (void)Success;
 174     assert(Success && "Malformed HSA Metadata");
 175   }
 176 }
 177
 178 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
 179   const MachineBasicBlock *MBB) const {
 180   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
 181     return false;
 182
 183   if (MBB->empty())
 184     return true;
 185
 186   // If this is a block implementing a long branch, an expression relative to
 187   // the start of the block is needed.  to the start of the block.
 188   // XXX - Is there a smarter way to check this?
 189   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
 190 }
 191
 192 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
 193   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
 194   if (!MFI.isEntryFunction())
 195     return;
 196
 197   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
 198   const Function &F = MF->getFunction();
 199   if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
 200       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
 201        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
 202     amd_kernel_code_t KernelCode;
 203     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
 204     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
 205   }
 206
 207   if (STM.isAmdHsaOS())
 208     HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
 209 }
 210
 211 void AMDGPUAsmPrinter::EmitFunctionBodyEnd() {
 212   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
 213   if (!MFI.isEntryFunction())
 214     return;
 215
 216   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI()) ||
 217       TM.getTargetTriple().getOS() != Triple::AMDHSA)
 218     return;
 219
 220   auto &Streamer = getTargetStreamer()->getStreamer();
 221   auto &Context = Streamer.getContext();
 222   auto &ObjectFileInfo = *Context.getObjectFileInfo();
 223   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
 224
 225   Streamer.PushSection();
 226   Streamer.SwitchSection(&ReadOnlySection);
 227
 228   // CP microcode requires the kernel descriptor to be allocated on 64 byte
 229   // alignment.
 230   Streamer.EmitValueToAlignment(64, 0, 1, 0);
 231   if (ReadOnlySection.getAlignment() < 64)
 232     ReadOnlySection.setAlignment(Align(64));
 233
 234   const MCSubtargetInfo &STI = MF->getSubtarget();
 235
 236   SmallString<128> KernelName;
 237   getNameWithPrefix(KernelName, &MF->getFunction());
 238   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
 239       STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
 240       CurrentProgramInfo.NumVGPRsForWavesPerEU,
 241       CurrentProgramInfo.NumSGPRsForWavesPerEU -
 242           IsaInfo::getNumExtraSGPRs(&STI,
 243                                     CurrentProgramInfo.VCCUsed,
 244                                     CurrentProgramInfo.FlatUsed),
 245       CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
 246       hasXNACK(STI));
 247
 248   Streamer.PopSection();
 249 }
 250
 251 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
 252   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) &&
 253       TM.getTargetTriple().getOS() == Triple::AMDHSA) {
 254     AsmPrinter::EmitFunctionEntryLabel();
 255     return;
 256   }
 257
 258   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
 259   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
 260   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
 261     SmallString<128> SymbolName;
 262     getNameWithPrefix(SymbolName, &MF->getFunction()),
 263     getTargetStreamer()->EmitAMDGPUSymbolType(
 264         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
 265   }
 266   if (DumpCodeInstEmitter) {
 267     // Disassemble function name label to text.
 268     DisasmLines.push_back(MF->getName().str() + ":");
 269     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
 270     HexLines.push_back("");
 271   }
 272
 273   AsmPrinter::EmitFunctionEntryLabel();
 274 }
 275
 276 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) {
 277   if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
 278     // Write a line for the basic block label if it is not only fallthrough.
 279     DisasmLines.push_back(
 280         (Twine("BB") + Twine(getFunctionNumber())
 281          + "_" + Twine(MBB.getNumber()) + ":").str());
 282     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
 283     HexLines.push_back("");
 284   }
 285   AsmPrinter::EmitBasicBlockStart(MBB);
 286 }
 287
 288 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
 289   if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
 290     if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
 291       OutContext.reportError({},
 292                              Twine(GV->getName()) +
 293                                  ": unsupported initializer for address space");
 294       return;
 295     }
 296
 297     // LDS variables aren't emitted in HSA or PAL yet.
 298     const Triple::OSType OS = TM.getTargetTriple().getOS();
 299     if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
 300       return;
 301
 302     MCSymbol *GVSym = getSymbol(GV);
 303
 304     GVSym->redefineIfPossible();
 305     if (GVSym->isDefined() || GVSym->isVariable())
 306       report_fatal_error("symbol '" + Twine(GVSym->getName()) +
 307                          "' is already defined");
 308
 309     const DataLayout &DL = GV->getParent()->getDataLayout();
 310     uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
 311     unsigned Align = GV->getAlignment();
 312     if (!Align)
 313       Align = 4;
 314
 315     EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
 316     EmitLinkage(GV, GVSym);
 317     if (auto TS = getTargetStreamer())
 318       TS->emitAMDGPULDS(GVSym, Size, Align);
 319     return;
 320   }
 321
 322   AsmPrinter::EmitGlobalVariable(GV);
 323 }
 324
 325 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
 326   CallGraphResourceInfo.clear();
 327
 328   // Pad with s_code_end to help tools and guard against instruction prefetch
 329   // causing stale data in caches. Arguably this should be done by the linker,
 330   // which is why this isn't done for Mesa.
 331   const MCSubtargetInfo &STI = *getGlobalSTI();
 332   if (AMDGPU::isGFX10(STI) &&
 333       (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
 334        STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
 335     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
 336     getTargetStreamer()->EmitCodeEnd();
 337   }
 338
 339   return AsmPrinter::doFinalization(M);
 340 }
 341
 342 // Print comments that apply to both callable functions and entry points.
 343 void AMDGPUAsmPrinter::emitCommonFunctionComments(
 344   uint32_t NumVGPR,
 345   uint32_t NumSGPR,
 346   uint64_t ScratchSize,
 347   uint64_t CodeSize,
 348   const AMDGPUMachineFunction *MFI) {
 349   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
 350   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
 351   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
 352   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
 353   OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
 354                               false);
 355 }
 356
 357 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
 358     const MachineFunction &MF) const {
 359   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
 360   uint16_t KernelCodeProperties = 0;
 361
 362   if (MFI.hasPrivateSegmentBuffer()) {
 363     KernelCodeProperties |=
 364         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
 365   }
 366   if (MFI.hasDispatchPtr()) {
 367     KernelCodeProperties |=
 368         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
 369   }
 370   if (MFI.hasQueuePtr()) {
 371     KernelCodeProperties |=
 372         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
 373   }
 374   if (MFI.hasKernargSegmentPtr()) {
 375     KernelCodeProperties |=
 376         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
 377   }
 378   if (MFI.hasDispatchID()) {
 379     KernelCodeProperties |=
 380         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
 381   }
 382   if (MFI.hasFlatScratchInit()) {
 383     KernelCodeProperties |=
 384         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 385   }
 386   if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
 387     KernelCodeProperties |=
 388         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
 389   }
 390
 391   return KernelCodeProperties;
 392 }
 393
 394 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
 395     const MachineFunction &MF,
 396     const SIProgramInfo &PI) const {
 397   amdhsa::kernel_descriptor_t KernelDescriptor;
 398   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
 399
 400   assert(isUInt<32>(PI.ScratchSize));
 401   assert(isUInt<32>(PI.ComputePGMRSrc1));
 402   assert(isUInt<32>(PI.ComputePGMRSrc2));
 403
 404   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
 405   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
 406   KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
 407   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
 408   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
 409
 410   return KernelDescriptor;
 411 }
 412
 413 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 414   CurrentProgramInfo = SIProgramInfo();
 415
 416   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
 417
 418   // The starting address of all shader programs must be 256 bytes aligned.
 419   // Regular functions just need the basic required instruction alignment.
 420   MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
 421
 422   SetupMachineFunction(MF);
 423
 424   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
 425   MCContext &Context = getObjFileLowering().getContext();
 426   // FIXME: This should be an explicit check for Mesa.
 427   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
 428     MCSectionELF *ConfigSection =
 429         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
 430     OutStreamer->SwitchSection(ConfigSection);
 431   }
 432
 433   if (MFI->isEntryFunction()) {
 434     getSIProgramInfo(CurrentProgramInfo, MF);
 435   } else {
 436     auto I = CallGraphResourceInfo.insert(
 437       std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
 438     SIFunctionResourceInfo &Info = I.first->second;
 439     assert(I.second && "should only be called once per function");
 440     Info = analyzeResourceUsage(MF);
 441   }
 442
 443   if (STM.isAmdPalOS())
 444     EmitPALMetadata(MF, CurrentProgramInfo);
 445   else if (!STM.isAmdHsaOS()) {
 446     EmitProgramInfoSI(MF, CurrentProgramInfo);
 447   }
 448
 449   DumpCodeInstEmitter = nullptr;
 450   if (STM.dumpCode()) {
 451     // For -dumpcode, get the assembler out of the streamer, even if it does
 452     // not really want to let us have it. This only works with -filetype=obj.
 453     bool SaveFlag = OutStreamer->getUseAssemblerInfoForParsing();
 454     OutStreamer->setUseAssemblerInfoForParsing(true);
 455     MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
 456     OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
 457     if (Assembler)
 458       DumpCodeInstEmitter = Assembler->getEmitterPtr();
 459   }
 460
 461   DisasmLines.clear();
 462   HexLines.clear();
 463   DisasmLineMaxLen = 0;
 464
 465   EmitFunctionBody();
 466
 467   if (isVerbose()) {
 468     MCSectionELF *CommentSection =
 469         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
 470     OutStreamer->SwitchSection(CommentSection);
 471
 472     if (!MFI->isEntryFunction()) {
 473       OutStreamer->emitRawComment(" Function info:", false);
 474       SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
 475       emitCommonFunctionComments(
 476         Info.NumVGPR,
 477         Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
 478         Info.PrivateSegmentSize,
 479         getFunctionCodeSize(MF), MFI);
 480       return false;
 481     }
 482
 483     OutStreamer->emitRawComment(" Kernel info:", false);
 484     emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
 485                                CurrentProgramInfo.NumSGPR,
 486                                CurrentProgramInfo.ScratchSize,
 487                                getFunctionCodeSize(MF), MFI);
 488
 489     OutStreamer->emitRawComment(
 490       " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
 491     OutStreamer->emitRawComment(
 492       " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
 493     OutStreamer->emitRawComment(
 494       " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
 495       " bytes/workgroup (compile time only)", false);
 496
 497     OutStreamer->emitRawComment(
 498       " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
 499     OutStreamer->emitRawComment(
 500       " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
 501
 502     OutStreamer->emitRawComment(
 503       " NumSGPRsForWavesPerEU: " +
 504       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
 505     OutStreamer->emitRawComment(
 506       " NumVGPRsForWavesPerEU: " +
 507       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
 508
 509     OutStreamer->emitRawComment(
 510       " Occupancy: " +
 511       Twine(CurrentProgramInfo.Occupancy), false);
 512
 513     OutStreamer->emitRawComment(
 514       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
 515
 516     OutStreamer->emitRawComment(
 517       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
 518       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
 519     OutStreamer->emitRawComment(
 520       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
 521       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
 522     OutStreamer->emitRawComment(
 523       " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
 524       Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
 525     OutStreamer->emitRawComment(
 526       " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
 527       Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
 528     OutStreamer->emitRawComment(
 529       " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
 530       Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
 531     OutStreamer->emitRawComment(
 532       " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
 533       Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
 534       false);
 535   }
 536
 537   if (DumpCodeInstEmitter) {
 538
 539     OutStreamer->SwitchSection(
 540         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
 541
 542     for (size_t i = 0; i < DisasmLines.size(); ++i) {
 543       std::string Comment = "\n";
 544       if (!HexLines[i].empty()) {
 545         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 546         Comment += " ; " + HexLines[i] + "\n";
 547       }
 548
 549       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
 550       OutStreamer->EmitBytes(StringRef(Comment));
 551     }
 552   }
 553
 554   return false;
 555 }
 556
 557 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
 558   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
 559   const SIInstrInfo *TII = STM.getInstrInfo();
 560
 561   uint64_t CodeSize = 0;
 562
 563   for (const MachineBasicBlock &MBB : MF) {
 564     for (const MachineInstr &MI : MBB) {
 565       // TODO: CodeSize should account for multiple functions.
 566
 567       // TODO: Should we count size of debug info?
 568       if (MI.isDebugInstr())
 569         continue;
 570
 571       CodeSize += TII->getInstSizeInBytes(MI);
 572     }
 573   }
 574
 575   return CodeSize;
 576 }
 577
 578 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
 579                                   const SIInstrInfo &TII,
 580                                   unsigned Reg) {
 581   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
 582     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
 583       return true;
 584   }
 585
 586   return false;
 587 }
 588
 589 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
 590   const GCNSubtarget &ST) const {
 591   return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
 592                                                      UsesVCC, UsesFlatScratch);
 593 }
 594
 595 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
 596   const MachineFunction &MF) const {
 597   SIFunctionResourceInfo Info;
 598
 599   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 600   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
 601   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
 602   const MachineRegisterInfo &MRI = MF.getRegInfo();
 603   const SIInstrInfo *TII = ST.getInstrInfo();
 604   const SIRegisterInfo &TRI = TII->getRegisterInfo();
 605
 606   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
 607                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
 608
 609   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
 610   // instructions aren't used to access the scratch buffer. Inline assembly may
 611   // need it though.
 612   //
 613   // If we only have implicit uses of flat_scr on flat instructions, it is not
 614   // really needed.
 615   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
 616       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
 617        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
 618        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
 619     Info.UsesFlatScratch = false;
 620   }
 621
 622   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
 623   Info.PrivateSegmentSize = FrameInfo.getStackSize();
 624   if (MFI->isStackRealigned())
 625     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
 626
 627
 628   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
 629                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
 630
 631   // If there are no calls, MachineRegisterInfo can tell us the used register
 632   // count easily.
 633   // A tail call isn't considered a call for MachineFrameInfo's purposes.
 634   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
 635     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
 636     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
 637       if (MRI.isPhysRegUsed(Reg)) {
 638         HighestVGPRReg = Reg;
 639         break;
 640       }
 641       MCPhysReg AReg = AMDGPU::AGPR0 + TRI.getHWRegIndex(Reg);
 642       if (MRI.isPhysRegUsed(AReg)) {
 643         HighestVGPRReg = AReg;
 644         break;
 645       }
 646     }
 647
 648     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
 649     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
 650       if (MRI.isPhysRegUsed(Reg)) {
 651         HighestSGPRReg = Reg;
 652         break;
 653       }
 654     }
 655
 656     // We found the maximum register index. They start at 0, so add one to get the
 657     // number of registers.
 658     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
 659       TRI.getHWRegIndex(HighestVGPRReg) + 1;
 660     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
 661       TRI.getHWRegIndex(HighestSGPRReg) + 1;
 662
 663     return Info;
 664   }
 665
 666   int32_t MaxVGPR = -1;
 667   int32_t MaxSGPR = -1;
 668   uint64_t CalleeFrameSize = 0;
 669
 670   for (const MachineBasicBlock &MBB : MF) {
 671     for (const MachineInstr &MI : MBB) {
 672       // TODO: Check regmasks? Do they occur anywhere except calls?
 673       for (const MachineOperand &MO : MI.operands()) {
 674         unsigned Width = 0;
 675         bool IsSGPR = false;
 676
 677         if (!MO.isReg())
 678           continue;
 679
 680         Register Reg = MO.getReg();
 681         switch (Reg) {
 682         case AMDGPU::EXEC:
 683         case AMDGPU::EXEC_LO:
 684         case AMDGPU::EXEC_HI:
 685         case AMDGPU::SCC:
 686         case AMDGPU::M0:
 687         case AMDGPU::SRC_SHARED_BASE:
 688         case AMDGPU::SRC_SHARED_LIMIT:
 689         case AMDGPU::SRC_PRIVATE_BASE:
 690         case AMDGPU::SRC_PRIVATE_LIMIT:
 691         case AMDGPU::SGPR_NULL:
 692           continue;
 693
 694         case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
 695           llvm_unreachable("src_pops_exiting_wave_id should not be used");
 696
 697         case AMDGPU::NoRegister:
 698           assert(MI.isDebugInstr());
 699           continue;
 700
 701         case AMDGPU::VCC:
 702         case AMDGPU::VCC_LO:
 703         case AMDGPU::VCC_HI:
 704           Info.UsesVCC = true;
 705           continue;
 706
 707         case AMDGPU::FLAT_SCR:
 708         case AMDGPU::FLAT_SCR_LO:
 709         case AMDGPU::FLAT_SCR_HI:
 710           continue;
 711
 712         case AMDGPU::XNACK_MASK:
 713         case AMDGPU::XNACK_MASK_LO:
 714         case AMDGPU::XNACK_MASK_HI:
 715           llvm_unreachable("xnack_mask registers should not be used");
 716
 717         case AMDGPU::LDS_DIRECT:
 718           llvm_unreachable("lds_direct register should not be used");
 719
 720         case AMDGPU::TBA:
 721         case AMDGPU::TBA_LO:
 722         case AMDGPU::TBA_HI:
 723         case AMDGPU::TMA:
 724         case AMDGPU::TMA_LO:
 725         case AMDGPU::TMA_HI:
 726           llvm_unreachable("trap handler registers should not be used");
 727
 728         case AMDGPU::SRC_VCCZ:
 729           llvm_unreachable("src_vccz register should not be used");
 730
 731         case AMDGPU::SRC_EXECZ:
 732           llvm_unreachable("src_execz register should not be used");
 733
 734         case AMDGPU::SRC_SCC:
 735           llvm_unreachable("src_scc register should not be used");
 736
 737         default:
 738           break;
 739         }
 740
 741         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
 742           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
 743                  "trap handler registers should not be used");
 744           IsSGPR = true;
 745           Width = 1;
 746         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
 747           IsSGPR = false;
 748           Width = 1;
 749         } else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
 750           IsSGPR = false;
 751           Width = 1;
 752         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
 753           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
 754                  "trap handler registers should not be used");
 755           IsSGPR = true;
 756           Width = 2;
 757         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
 758           IsSGPR = false;
 759           Width = 2;
 760         } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
 761           IsSGPR = false;
 762           Width = 2;
 763         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
 764           IsSGPR = false;
 765           Width = 3;
 766         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
 767           Width = 3;
 768         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
 769           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
 770             "trap handler registers should not be used");
 771           IsSGPR = true;
 772           Width = 4;
 773         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
 774           IsSGPR = false;
 775           Width = 4;
 776         } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
 777           IsSGPR = false;
 778           Width = 4;
 779         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
 780           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
 781             "trap handler registers should not be used");
 782           IsSGPR = true;
 783           Width = 8;
 784         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
 785           IsSGPR = false;
 786           Width = 8;
 787         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
 788           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
 789             "trap handler registers should not be used");
 790           IsSGPR = true;
 791           Width = 16;
 792         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
 793           IsSGPR = false;
 794           Width = 16;
 795         } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
 796           IsSGPR = false;
 797           Width = 16;
 798         } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
 799           IsSGPR = true;
 800           Width = 32;
 801         } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
 802           IsSGPR = false;
 803           Width = 32;
 804         } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
 805           IsSGPR = false;
 806           Width = 32;
 807         } else {
 808           llvm_unreachable("Unknown register class");
 809         }
 810         unsigned HWReg = TRI.getHWRegIndex(Reg);
 811         int MaxUsed = HWReg + Width - 1;
 812         if (IsSGPR) {
 813           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
 814         } else {
 815           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
 816         }
 817       }
 818
 819       if (MI.isCall()) {
 820         // Pseudo used just to encode the underlying global. Is there a better
 821         // way to track this?
 822
 823         const MachineOperand *CalleeOp
 824           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
 825         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
 826         if (Callee->isDeclaration()) {
 827           // If this is a call to an external function, we can't do much. Make
 828           // conservative guesses.
 829
 830           // 48 SGPRs - vcc, - flat_scr, -xnack
 831           int MaxSGPRGuess =
 832             47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
 833           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
 834           MaxVGPR = std::max(MaxVGPR, 23);
 835
 836           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
 837           Info.UsesVCC = true;
 838           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
 839           Info.HasDynamicallySizedStack = true;
 840         } else {
 841           // We force CodeGen to run in SCC order, so the callee's register
 842           // usage etc. should be the cumulative usage of all callees.
 843
 844           auto I = CallGraphResourceInfo.find(Callee);
 845           if (I == CallGraphResourceInfo.end()) {
 846             // Avoid crashing on undefined behavior with an illegal call to a
 847             // kernel. If a callsite's calling convention doesn't match the
 848             // function's, it's undefined behavior. If the callsite calling
 849             // convention does match, that would have errored earlier.
 850             // FIXME: The verifier shouldn't allow this.
 851             if (AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
 852               report_fatal_error("invalid call to entry function");
 853
 854             llvm_unreachable("callee should have been handled before caller");
 855           }
 856
 857           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
 858           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
 859           CalleeFrameSize
 860             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
 861           Info.UsesVCC |= I->second.UsesVCC;
 862           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
 863           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
 864           Info.HasRecursion |= I->second.HasRecursion;
 865         }
 866
 867         if (!Callee->doesNotRecurse())
 868           Info.HasRecursion = true;
 869       }
 870     }
 871   }
 872
 873   Info.NumExplicitSGPR = MaxSGPR + 1;
 874   Info.NumVGPR = MaxVGPR + 1;
 875   Info.PrivateSegmentSize += CalleeFrameSize;
 876
 877   return Info;
 878 }
 879
 880 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 881                                         const MachineFunction &MF) {
 882   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
 883
 884   ProgInfo.NumVGPR = Info.NumVGPR;
 885   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
 886   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
 887   ProgInfo.VCCUsed = Info.UsesVCC;
 888   ProgInfo.FlatUsed = Info.UsesFlatScratch;
 889   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
 890
 891   if (!isUInt<32>(ProgInfo.ScratchSize)) {
 892     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
 893                                           ProgInfo.ScratchSize, DS_Error);
 894     MF.getFunction().getContext().diagnose(DiagStackSize);
 895   }
 896
 897   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
 898   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 899
 900   // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
 901   // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
 902   // unified.
 903   unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
 904       &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
 905
 906   // Check the addressable register limit before we add ExtraSGPRs.
 907   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
 908       !STM.hasSGPRInitBug()) {
 909     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
 910     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
 911       // This can happen due to a compiler bug or when using inline asm.
 912       LLVMContext &Ctx = MF.getFunction().getContext();
 913       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
 914                                        "addressable scalar registers",
 915                                        ProgInfo.NumSGPR, DS_Error,
 916                                        DK_ResourceLimit,
 917                                        MaxAddressableNumSGPRs);
 918       Ctx.diagnose(Diag);
 919       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
 920     }
 921   }
 922
 923   // Account for extra SGPRs and VGPRs reserved for debugger use.
 924   ProgInfo.NumSGPR += ExtraSGPRs;
 925
 926   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
 927   // dispatch registers are function args.
 928   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
 929   for (auto &Arg : MF.getFunction().args()) {
 930     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
 931     if (Arg.hasAttribute(Attribute::InReg))
 932       WaveDispatchNumSGPR += NumRegs;
 933     else
 934       WaveDispatchNumVGPR += NumRegs;
 935   }
 936   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
 937   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
 938
 939   // Adjust number of registers used to meet default/requested minimum/maximum
 940   // number of waves per execution unit request.
 941   ProgInfo.NumSGPRsForWavesPerEU = std::max(
 942     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
 943   ProgInfo.NumVGPRsForWavesPerEU = std::max(
 944     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
 945
 946   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
 947       STM.hasSGPRInitBug()) {
 948     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
 949     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
 950       // This can happen due to a compiler bug or when using inline asm to use
 951       // the registers which are usually reserved for vcc etc.
 952       LLVMContext &Ctx = MF.getFunction().getContext();
 953       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
 954                                        "scalar registers",
 955                                        ProgInfo.NumSGPR, DS_Error,
 956                                        DK_ResourceLimit,
 957                                        MaxAddressableNumSGPRs);
 958       Ctx.diagnose(Diag);
 959       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
 960       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
 961     }
 962   }
 963
 964   if (STM.hasSGPRInitBug()) {
 965     ProgInfo.NumSGPR =
 966         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
 967     ProgInfo.NumSGPRsForWavesPerEU =
 968         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
 969   }
 970
 971   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
 972     LLVMContext &Ctx = MF.getFunction().getContext();
 973     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
 974                                      MFI->getNumUserSGPRs(), DS_Error);
 975     Ctx.diagnose(Diag);
 976   }
 977
 978   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
 979     LLVMContext &Ctx = MF.getFunction().getContext();
 980     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
 981                                      MFI->getLDSSize(), DS_Error);
 982     Ctx.diagnose(Diag);
 983   }
 984
 985   ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
 986       &STM, ProgInfo.NumSGPRsForWavesPerEU);
 987   ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
 988       &STM, ProgInfo.NumVGPRsForWavesPerEU);
 989
 990   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
 991   // register.
 992   ProgInfo.FloatMode = getFPMode(MF);
 993
 994   const SIModeRegisterDefaults Mode = MFI->getMode();
 995   ProgInfo.IEEEMode = Mode.IEEE;
 996
 997   // Make clamp modifier on NaN input returns 0.
 998   ProgInfo.DX10Clamp = Mode.DX10Clamp;
 999
1000   unsigned LDSAlignShift;
1001   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1002     // LDS is allocated in 64 dword blocks.
1003     LDSAlignShift = 8;
1004   } else {
1005     // LDS is allocated in 128 dword blocks.
1006     LDSAlignShift = 9;
1007   }
1008
1009   unsigned LDSSpillSize =
1010     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
1011
1012   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
1013   ProgInfo.LDSBlocks =
1014       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1015
1016   // Scratch is allocated in 256 dword blocks.
1017   unsigned ScratchAlignShift = 10;
1018   // We need to program the hardware with the amount of scratch memory that
1019   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
1020   // scratch memory used per thread.
1021   ProgInfo.ScratchBlocks =
1022       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
1023               1ULL << ScratchAlignShift) >>
1024       ScratchAlignShift;
1025
1026   if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
1027     ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1028     ProgInfo.MemOrdered = 1;
1029   }
1030
1031   ProgInfo.ComputePGMRSrc1 =
1032       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
1033       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
1034       S_00B848_PRIORITY(ProgInfo.Priority) |
1035       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
1036       S_00B848_PRIV(ProgInfo.Priv) |
1037       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
1038       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
1039       S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
1040       S_00B848_WGP_MODE(ProgInfo.WgpMode) |
1041       S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
1042
1043   // 0 = X, 1 = XY, 2 = XYZ
1044   unsigned TIDIGCompCnt = 0;
1045   if (MFI->hasWorkItemIDZ())
1046     TIDIGCompCnt = 2;
1047   else if (MFI->hasWorkItemIDY())
1048     TIDIGCompCnt = 1;
1049
1050   ProgInfo.ComputePGMRSrc2 =
1051       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
1052       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
1053       // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1054       S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
1055       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
1056       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
1057       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
1058       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
1059       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
1060       S_00B84C_EXCP_EN_MSB(0) |
1061       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1062       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
1063       S_00B84C_EXCP_EN(0);
1064
1065   ProgInfo.Occupancy = STM.computeOccupancy(MF, ProgInfo.LDSSize,
1066                                             ProgInfo.NumSGPRsForWavesPerEU,
1067                                             ProgInfo.NumVGPRsForWavesPerEU);
1068 }
1069
1070 static unsigned getRsrcReg(CallingConv::ID CallConv) {
1071   switch (CallConv) {
1072   default: LLVM_FALLTHROUGH;
1073   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1074   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1075   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1076   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1077   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1078   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1079   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1080   }
1081 }
1082
1083 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1084                                          const SIProgramInfo &CurrentProgramInfo) {
1085   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1086   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1087
1088   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1089     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1090
1091     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1092
1093     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1094     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1095
1096     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1097     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1098
1099     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1100     // 0" comment but I don't see a corresponding field in the register spec.
1101   } else {
1102     OutStreamer->EmitIntValue(RsrcReg, 4);
1103     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1104                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1105     OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1106     OutStreamer->EmitIntValue(
1107         S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1108   }
1109
1110   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1111     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1112     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1113     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1114     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1115     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1116     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1117   }
1118
1119   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1120   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1121   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1122   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1123 }
1124
1125 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1126 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1127 // metadata items into the PALMD::Metadata, combining with any provided by the
1128 // frontend as LLVM metadata. Once all functions are written, the PAL metadata
1129 // is then written as a single block in the .note section.
1130 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1131        const SIProgramInfo &CurrentProgramInfo) {
1132   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1133   auto CC = MF.getFunction().getCallingConv();
1134   auto MD = getTargetStreamer()->getPALMetadata();
1135
1136   MD->setEntryPoint(CC, MF.getFunction().getName());
1137   MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1138   MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1139   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1140     MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
1141     MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1142   } else {
1143     MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1144         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
1145     if (CurrentProgramInfo.ScratchBlocks > 0)
1146       MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1147   }
1148   // ScratchSize is in bytes, 16 aligned.
1149   MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1150   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1151     MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1152     MD->setSpiPsInputEna(MFI->getPSInputEnable());
1153     MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1154   }
1155
1156   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1157   if (STM.isWave32())
1158     MD->setWave32(MF.getFunction().getCallingConv());
1159 }
1160
1161 // This is supposed to be log2(Size)
1162 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1163   switch (Size) {
1164   case 4:
1165     return AMD_ELEMENT_4_BYTES;
1166   case 8:
1167     return AMD_ELEMENT_8_BYTES;
1168   case 16:
1169     return AMD_ELEMENT_16_BYTES;
1170   default:
1171     llvm_unreachable("invalid private_element_size");
1172   }
1173 }
1174
1175 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1176                                         const SIProgramInfo &CurrentProgramInfo,
1177                                         const MachineFunction &MF) const {
1178   const Function &F = MF.getFunction();
1179   assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1180          F.getCallingConv() == CallingConv::SPIR_KERNEL);
1181
1182   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1183   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1184
1185   AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
1186
1187   Out.compute_pgm_resource_registers =
1188       CurrentProgramInfo.ComputePGMRSrc1 |
1189       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1190   Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
1191
1192   if (CurrentProgramInfo.DynamicCallStack)
1193     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1194
1195   AMD_HSA_BITS_SET(Out.code_properties,
1196                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1197                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1198
1199   if (MFI->hasPrivateSegmentBuffer()) {
1200     Out.code_properties |=
1201       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1202   }
1203
1204   if (MFI->hasDispatchPtr())
1205     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1206
1207   if (MFI->hasQueuePtr())
1208     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1209
1210   if (MFI->hasKernargSegmentPtr())
1211     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1212
1213   if (MFI->hasDispatchID())
1214     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1215
1216   if (MFI->hasFlatScratchInit())
1217     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1218
1219   if (MFI->hasDispatchPtr())
1220     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1221
1222   if (STM.isXNACKEnabled())
1223     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1224
1225   unsigned MaxKernArgAlign;
1226   Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1227   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1228   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1229   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1230   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1231
1232   // These alignment values are specified in powers of two, so alignment =
1233   // 2^n.  The minimum alignment is 2^4 = 16.
1234   Out.kernarg_segment_alignment = std::max<size_t>(4,
1235       countTrailingZeros(MaxKernArgAlign));
1236 }
1237
1238 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1239                                        const char *ExtraCode, raw_ostream &O) {
1240   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1241   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1242     return false;
1243
1244   if (ExtraCode && ExtraCode[0]) {
1245     if (ExtraCode[1] != 0)
1246       return true; // Unknown modifier.
1247
1248     switch (ExtraCode[0]) {
1249     case 'r':
1250       break;
1251     default:
1252       return true;
1253     }
1254   }
1255
1256   // TODO: Should be able to support other operand types like globals.
1257   const MachineOperand &MO = MI->getOperand(OpNo);
1258   if (MO.isReg()) {
1259     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1260                                        *MF->getSubtarget().getRegisterInfo());
1261     return false;
1262   }
1263
1264   return true;
1265 }