lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def

   1 //===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file defines all the static objects used by AMDGPURegisterBankInfo.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 namespace llvm {
  14 namespace AMDGPU {
  15
  16 enum PartialMappingIdx {
  17   None = - 1,
  18   PM_SGPR1  = 2,
  19   PM_SGPR16 = 6,
  20   PM_SGPR32 = 7,
  21   PM_SGPR64 = 8,
  22   PM_SGPR128 = 9,
  23   PM_SGPR256 = 10,
  24   PM_SGPR512 = 11,
  25   PM_VGPR1  = 12,
  26   PM_VGPR16 = 16,
  27   PM_VGPR32 = 17,
  28   PM_VGPR64 = 18,
  29   PM_VGPR128 = 19,
  30   PM_VGPR256 = 20,
  31   PM_VGPR512 = 21,
  32   PM_SGPR96 = 22,
  33   PM_VGPR96 = 23
  34 };
  35
  36 const RegisterBankInfo::PartialMapping PartMappings[] {
  37   // StartIdx, Length, RegBank
  38   {0, 1,  SCCRegBank},
  39   {0, 1,  VCCRegBank},
  40
  41   {0, 1,  SGPRRegBank}, // SGPR begin
  42   {0, 16, SGPRRegBank},
  43   {0, 32, SGPRRegBank},
  44   {0, 64, SGPRRegBank},
  45   {0, 128, SGPRRegBank},
  46   {0, 256, SGPRRegBank},
  47   {0, 512, SGPRRegBank},
  48
  49   {0, 1,  VGPRRegBank}, // VGPR begin
  50   {0, 16, VGPRRegBank},
  51   {0, 32, VGPRRegBank},
  52   {0, 64, VGPRRegBank},
  53   {0, 128, VGPRRegBank},
  54   {0, 256, VGPRRegBank},
  55   {0, 512, VGPRRegBank},
  56   {0, 96, SGPRRegBank},
  57   {0, 96, VGPRRegBank},
  58 };
  59
  60 const RegisterBankInfo::ValueMapping ValMappings[] {
  61   // SCC
  62   {&PartMappings[0], 1},
  63
  64   // VCC
  65   {&PartMappings[1], 1},
  66
  67   // SGPRs
  68   {&PartMappings[2], 1},
  69   {nullptr, 0}, // Illegal power of 2 sizes
  70   {nullptr, 0},
  71   {nullptr, 0},
  72   {&PartMappings[3], 1},
  73   {&PartMappings[4], 1},
  74   {&PartMappings[5], 1},
  75   {&PartMappings[6], 1},
  76   {&PartMappings[7], 1},
  77   {&PartMappings[8], 1},
  78
  79     // VGPRs
  80   {&PartMappings[9], 1},
  81   {nullptr, 0},
  82   {nullptr, 0},
  83   {nullptr, 0},
  84   {&PartMappings[10], 1},
  85   {&PartMappings[11], 1},
  86   {&PartMappings[12], 1},
  87   {&PartMappings[13], 1},
  88   {&PartMappings[14], 1},
  89   {&PartMappings[15], 1},
  90   {&PartMappings[16], 1},
  91   {&PartMappings[17], 1}
  92 };
  93
  94 const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
  95   {0, 32, SGPRRegBank}, // 32-bit op
  96   {0, 32, SGPRRegBank}, // 2x32-bit op
  97   {32, 32, SGPRRegBank},
  98   {0, 64, SGPRRegBank}, // <2x32-bit> op
  99
 100   {0, 32, VGPRRegBank}, // 32-bit op
 101   {0, 32, VGPRRegBank}, // 2x32-bit op
 102   {32, 32, VGPRRegBank},
 103 };
 104
 105
 106 // For some instructions which can operate 64-bit only for the scalar version.
 107 const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
 108   /*32-bit sgpr*/     {&SGPROnly64BreakDown[0], 1},
 109   /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
 110   /*64-bit sgpr */    {&SGPROnly64BreakDown[3], 1},
 111
 112   /*32-bit vgpr*/     {&SGPROnly64BreakDown[4], 1},
 113   /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
 114 };
 115
 116 enum ValueMappingIdx {
 117   SCCStartIdx = 0,
 118   SGPRStartIdx = 2,
 119   VGPRStartIdx = 12
 120 };
 121
 122 const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
 123                                                       unsigned Size) {
 124   unsigned Idx;
 125   switch (Size) {
 126   case 1:
 127     if (BankID == AMDGPU::SCCRegBankID)
 128       return &ValMappings[0];
 129     if (BankID == AMDGPU::VCCRegBankID)
 130       return &ValMappings[1];
 131
 132     // 1-bit values not from a compare etc.
 133     Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
 134     break;
 135   case 96:
 136     assert(BankID != AMDGPU::VCCRegBankID);
 137     Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
 138     break;
 139   default:
 140     assert(BankID != AMDGPU::VCCRegBankID);
 141     Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
 142     Idx += Log2_32_Ceil(Size);
 143     break;
 144   }
 145
 146   assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
 147   assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
 148
 149   return &ValMappings[Idx];
 150 }
 151
 152 const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
 153                                                                 unsigned Size) {
 154   if (Size != 64)
 155     return getValueMapping(BankID, Size);
 156
 157   if (BankID == AMDGPU::VGPRRegBankID)
 158     return &ValMappingsSGPR64OnlyVGPR32[4];
 159
 160   assert(BankID == AMDGPU::SGPRRegBankID);
 161   return &ValMappingsSGPR64OnlyVGPR32[2];
 162 }
 163
 164 const RegisterBankInfo::PartialMapping LoadSGPROnlyBreakDown[] {
 165   /* 256-bit load */    {0, 256, SGPRRegBank},
 166   /* 512-bit load */    {0, 512, SGPRRegBank},
 167   /* 8 32-bit loads */  {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
 168                         {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
 169                         {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
 170                         {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
 171   /* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
 172                         {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
 173                         {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
 174                         {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
 175                         {256, 32, VGPRRegBank}, {288, 32, VGPRRegBank},
 176                         {320, 32, VGPRRegBank}, {352, 32, VGPRRegBank},
 177                         {384, 32, VGPRRegBank}, {416, 32, VGPRRegBank},
 178                         {448, 32, VGPRRegBank}, {480, 32, VGPRRegBank},
 179   /* 4 64-bit loads */  {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
 180                         {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
 181   /* 8 64-bit loads */  {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
 182                         {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
 183                         {256, 64, VGPRRegBank}, {320, 64, VGPRRegBank},
 184                         {384, 64, VGPRRegBank}, {448, 64, VGPRRegBank},
 185
 186   /* FIXME: The generic register bank select does not support complex
 187    * break downs where the number of vector elements does not equal the
 188    * number of breakdowns.
 189    * FIXME: register bank select now tries to handle complex break downs,
 190    * but it emits an illegal instruction:
 191    * %1:vgpr(<8 x s32>) = G_CONCAT_VECTORS %2:vgpr(s128), %3:vgpr(s128)
 192    */
 193   /* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
 194   /* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
 195                         {256, 128, VGPRRegBank}, {384, 128, VGPRRegBank}
 196 };
 197
 198 const RegisterBankInfo::ValueMapping ValMappingsLoadSGPROnly[] {
 199   /* 256-bit load */     {&LoadSGPROnlyBreakDown[0], 1},
 200   /* 512-bit load */     {&LoadSGPROnlyBreakDown[1], 1},
 201   /* <8 x i32> load  */  {&LoadSGPROnlyBreakDown[2], 8},
 202   /* <16 x i32> load */  {&LoadSGPROnlyBreakDown[10], 16},
 203   /* <4 x i64> load */   {&LoadSGPROnlyBreakDown[26], 4},
 204   /* <8 x i64> load */   {&LoadSGPROnlyBreakDown[30], 8}
 205 };
 206
 207 const RegisterBankInfo::ValueMapping *
 208 getValueMappingLoadSGPROnly(unsigned BankID, LLT SizeTy) {
 209   unsigned Size = SizeTy.getSizeInBits();
 210   if (Size < 256 || BankID == AMDGPU::SGPRRegBankID)
 211     return getValueMapping(BankID, Size);
 212
 213   assert((Size == 256 || Size == 512) && BankID == AMDGPU::VGPRRegBankID);
 214
 215   // Default to using the non-split ValueMappings, we will use these if
 216   // the register bank is SGPR or if we don't know how to handle the vector
 217   // type.
 218   unsigned Idx = Size == 256 ? 0 : 1;
 219
 220   // We need to split this load if it has a vgpr pointer.
 221   if (BankID == AMDGPU::VGPRRegBankID) {
 222     if (SizeTy == LLT::vector(8, 32))
 223       Idx = 2;
 224     else if (SizeTy == LLT::vector(16, 32))
 225       Idx = 3;
 226     else if (SizeTy == LLT::vector(4, 64))
 227       Idx = 4;
 228     else if (SizeTy == LLT::vector(8, 64))
 229       Idx = 5;
 230   }
 231
 232   return &ValMappingsLoadSGPROnly[Idx];
 233 }
 234
 235
 236 } // End AMDGPU namespace.
 237 } // End llvm namespace.