lib/Target/AMDGPU/AMDGPULegalizerInfo.h

   1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the Machinelegalizer class for
  10 /// AMDGPU.
  11 /// \todo This should be generated by TableGen.
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
  15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
  16
  17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  18 #include "AMDGPUArgumentUsageInfo.h"
  19 #include "SIInstrInfo.h"
  20
  21 namespace llvm {
  22
  23 class GCNTargetMachine;
  24 class LLVMContext;
  25 class GCNSubtarget;
  26
  27 /// This class provides the information for the target register banks.
  28 class AMDGPULegalizerInfo : public LegalizerInfo {
  29   const GCNSubtarget &ST;
  30
  31 public:
  32   AMDGPULegalizerInfo(const GCNSubtarget &ST,
  33                       const GCNTargetMachine &TM);
  34
  35   bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
  36                       MachineIRBuilder &B,
  37                       GISelChangeObserver &Observer) const override;
  38
  39   Register getSegmentAperture(unsigned AddrSpace,
  40                               MachineRegisterInfo &MRI,
  41                               MachineIRBuilder &B) const;
  42
  43   bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
  44                              MachineIRBuilder &B) const;
  45   bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
  46                      MachineIRBuilder &B) const;
  47   bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
  48                      MachineIRBuilder &B) const;
  49   bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
  50                               MachineIRBuilder &B) const;
  51   bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
  52                      MachineIRBuilder &B, bool Signed) const;
  53   bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
  54                             MachineIRBuilder &B) const;
  55   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
  56                                 MachineIRBuilder &B) const;
  57   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
  58                                MachineIRBuilder &B) const;
  59   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
  60                       MachineIRBuilder &B) const;
  61
  62   bool buildPCRelGlobalAddress(
  63     Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
  64     unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
  65
  66   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
  67                            MachineIRBuilder &B) const;
  68   bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
  69                     MachineIRBuilder &B,
  70                     GISelChangeObserver &Observer) const;
  71
  72   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
  73                     MachineIRBuilder &B) const;
  74
  75   Register getLiveInRegister(MachineRegisterInfo &MRI,
  76                              Register Reg, LLT Ty) const;
  77
  78   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
  79                       const ArgDescriptor *Arg) const;
  80   bool legalizePreloadedArgIntrin(
  81     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
  82     AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
  83
  84   bool legalizeFDIVFast(MachineInstr &MI, MachineRegisterInfo &MRI,
  85                         MachineIRBuilder &B) const;
  86
  87   bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
  88                               MachineIRBuilder &B) const;
  89   bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
  90                            MachineIRBuilder &B, unsigned AddrSpace) const;
  91
  92   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
  93                           Register Reg) const;
  94   bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
  95                               MachineIRBuilder &B, bool IsFormat) const;
  96   bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
  97                          MachineIRBuilder &B) const override;
  98
  99 };
 100 } // End llvm namespace.
 101 #endif