lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

   1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 //
  14
  15 #include "AMDGPUAsmPrinter.h"
  16 #include "AMDGPUSubtarget.h"
  17 #include "AMDGPUTargetMachine.h"
  18 #include "MCTargetDesc/AMDGPUInstPrinter.h"
  19 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  20 #include "R600AsmPrinter.h"
  21 #include "SIInstrInfo.h"
  22 #include "llvm/CodeGen/MachineBasicBlock.h"
  23 #include "llvm/CodeGen/MachineInstr.h"
  24 #include "llvm/IR/Constants.h"
  25 #include "llvm/IR/Function.h"
  26 #include "llvm/IR/GlobalVariable.h"
  27 #include "llvm/MC/MCCodeEmitter.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCExpr.h"
  30 #include "llvm/MC/MCInst.h"
  31 #include "llvm/MC/MCObjectStreamer.h"
  32 #include "llvm/MC/MCStreamer.h"
  33 #include "llvm/Support/ErrorHandling.h"
  34 #include "llvm/Support/Format.h"
  35 #include <algorithm>
  36
  37 using namespace llvm;
  38
  39 namespace {
  40
  41 class AMDGPUMCInstLower {
  42   MCContext &Ctx;
  43   const TargetSubtargetInfo &ST;
  44   const AsmPrinter &AP;
  45
  46   const MCExpr *getLongBranchBlockExpr(const MachineBasicBlock &SrcBB,
  47                                        const MachineOperand &MO) const;
  48
  49 public:
  50   AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
  51                     const AsmPrinter &AP);
  52
  53   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
  54
  55   /// Lower a MachineInstr to an MCInst
  56   void lower(const MachineInstr *MI, MCInst &OutMI) const;
  57
  58 };
  59
  60 class R600MCInstLower : public AMDGPUMCInstLower {
  61 public:
  62   R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
  63                   const AsmPrinter &AP);
  64
  65   /// Lower a MachineInstr to an MCInst
  66   void lower(const MachineInstr *MI, MCInst &OutMI) const;
  67 };
  68
  69
  70 } // End anonymous namespace
  71
  72 #include "AMDGPUGenMCPseudoLowering.inc"
  73
  74 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
  75                                      const TargetSubtargetInfo &st,
  76                                      const AsmPrinter &ap):
  77   Ctx(ctx), ST(st), AP(ap) { }
  78
  79 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
  80   switch (MOFlags) {
  81   default:
  82     return MCSymbolRefExpr::VK_None;
  83   case SIInstrInfo::MO_GOTPCREL:
  84     return MCSymbolRefExpr::VK_GOTPCREL;
  85   case SIInstrInfo::MO_GOTPCREL32_LO:
  86     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
  87   case SIInstrInfo::MO_GOTPCREL32_HI:
  88     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
  89   case SIInstrInfo::MO_REL32_LO:
  90     return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
  91   case SIInstrInfo::MO_REL32_HI:
  92     return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
  93   case SIInstrInfo::MO_ABS32_LO:
  94     return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
  95   case SIInstrInfo::MO_ABS32_HI:
  96     return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
  97   }
  98 }
  99
 100 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
 101   const MachineBasicBlock &SrcBB,
 102   const MachineOperand &MO) const {
 103   const MCExpr *DestBBSym
 104     = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
 105   const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
 106
 107   // FIXME: The first half of this assert should be removed. This should
 108   // probably be PC relative instead of using the source block symbol, and
 109   // therefore the indirect branch expansion should use a bundle.
 110   assert(
 111       skipDebugInstructionsForward(SrcBB.begin(), SrcBB.end())->getOpcode() ==
 112           AMDGPU::S_GETPC_B64 &&
 113       ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
 114
 115   // s_getpc_b64 returns the address of next instruction.
 116   const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
 117   SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
 118
 119   if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD)
 120     return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
 121
 122   assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD);
 123   return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
 124 }
 125
 126 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
 127                                      MCOperand &MCOp) const {
 128   switch (MO.getType()) {
 129   default:
 130     llvm_unreachable("unknown operand type");
 131   case MachineOperand::MO_Immediate:
 132     MCOp = MCOperand::createImm(MO.getImm());
 133     return true;
 134   case MachineOperand::MO_Register:
 135     MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
 136     return true;
 137   case MachineOperand::MO_MachineBasicBlock: {
 138     if (MO.getTargetFlags() != 0) {
 139       MCOp = MCOperand::createExpr(
 140         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
 141     } else {
 142       MCOp = MCOperand::createExpr(
 143         MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
 144     }
 145
 146     return true;
 147   }
 148   case MachineOperand::MO_GlobalAddress: {
 149     const GlobalValue *GV = MO.getGlobal();
 150     SmallString<128> SymbolName;
 151     AP.getNameWithPrefix(SymbolName, GV);
 152     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
 153     const MCExpr *Expr =
 154       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
 155     int64_t Offset = MO.getOffset();
 156     if (Offset != 0) {
 157       Expr = MCBinaryExpr::createAdd(Expr,
 158                                      MCConstantExpr::create(Offset, Ctx), Ctx);
 159     }
 160     MCOp = MCOperand::createExpr(Expr);
 161     return true;
 162   }
 163   case MachineOperand::MO_ExternalSymbol: {
 164     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
 165     Sym->setExternal(true);
 166     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
 167     MCOp = MCOperand::createExpr(Expr);
 168     return true;
 169   }
 170   case MachineOperand::MO_RegisterMask:
 171     // Regmasks are like implicit defs.
 172     return false;
 173   }
 174 }
 175
 176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
 177   unsigned Opcode = MI->getOpcode();
 178   const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
 179
 180   // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
 181   // need to select it to the subtarget specific version, and there's no way to
 182   // do that with a single pseudo source operation.
 183   if (Opcode == AMDGPU::S_SETPC_B64_return)
 184     Opcode = AMDGPU::S_SETPC_B64;
 185   else if (Opcode == AMDGPU::SI_CALL) {
 186     // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
 187     // called function (which we need to remove here).
 188     OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
 189     MCOperand Dest, Src;
 190     lowerOperand(MI->getOperand(0), Dest);
 191     lowerOperand(MI->getOperand(1), Src);
 192     OutMI.addOperand(Dest);
 193     OutMI.addOperand(Src);
 194     return;
 195   } else if (Opcode == AMDGPU::SI_TCRETURN) {
 196     // TODO: How to use branch immediate and avoid register+add?
 197     Opcode = AMDGPU::S_SETPC_B64;
 198   }
 199
 200   int MCOpcode = TII->pseudoToMCOpcode(Opcode);
 201   if (MCOpcode == -1) {
 202     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
 203     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
 204                 "a target-specific version: " + Twine(MI->getOpcode()));
 205   }
 206
 207   OutMI.setOpcode(MCOpcode);
 208
 209   for (const MachineOperand &MO : MI->explicit_operands()) {
 210     MCOperand MCOp;
 211     lowerOperand(MO, MCOp);
 212     OutMI.addOperand(MCOp);
 213   }
 214 }
 215
 216 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
 217                                     MCOperand &MCOp) const {
 218   const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
 219   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
 220   return MCInstLowering.lowerOperand(MO, MCOp);
 221 }
 222
 223 static const MCExpr *lowerAddrSpaceCast(const TargetMachine &TM,
 224                                         const Constant *CV,
 225                                         MCContext &OutContext) {
 226   // TargetMachine does not support llvm-style cast. Use C++-style cast.
 227   // This is safe since TM is always of type AMDGPUTargetMachine or its
 228   // derived class.
 229   auto &AT = static_cast<const AMDGPUTargetMachine&>(TM);
 230   auto *CE = dyn_cast<ConstantExpr>(CV);
 231
 232   // Lower null pointers in private and local address space.
 233   // Clang generates addrspacecast for null pointers in private and local
 234   // address space, which needs to be lowered.
 235   if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
 236     auto Op = CE->getOperand(0);
 237     auto SrcAddr = Op->getType()->getPointerAddressSpace();
 238     if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
 239       auto DstAddr = CE->getType()->getPointerAddressSpace();
 240       return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
 241         OutContext);
 242     }
 243   }
 244   return nullptr;
 245 }
 246
 247 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
 248   if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
 249     return E;
 250   return AsmPrinter::lowerConstant(CV);
 251 }
 252
 253 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
 254   if (emitPseudoExpansionLowering(*OutStreamer, MI))
 255     return;
 256
 257   const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
 258   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
 259
 260   StringRef Err;
 261   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
 262     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
 263     C.emitError("Illegal instruction detected: " + Err);
 264     MI->print(errs());
 265   }
 266
 267   if (MI->isBundle()) {
 268     const MachineBasicBlock *MBB = MI->getParent();
 269     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
 270     while (I != MBB->instr_end() && I->isInsideBundle()) {
 271       EmitInstruction(&*I);
 272       ++I;
 273     }
 274   } else {
 275     // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
 276     // placeholder terminator instructions and should only be printed as
 277     // comments.
 278     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
 279       if (isVerbose()) {
 280         SmallVector<char, 16> BBStr;
 281         raw_svector_ostream Str(BBStr);
 282
 283         const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
 284         const MCSymbolRefExpr *Expr
 285           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
 286         Expr->print(Str, MAI);
 287         OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
 288       }
 289
 290       return;
 291     }
 292
 293     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
 294       if (isVerbose())
 295         OutStreamer->emitRawComment(" return to shader part epilog");
 296       return;
 297     }
 298
 299     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
 300       if (isVerbose())
 301         OutStreamer->emitRawComment(" wave barrier");
 302       return;
 303     }
 304
 305     if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
 306       if (isVerbose())
 307         OutStreamer->emitRawComment(" divergent unreachable");
 308       return;
 309     }
 310
 311     MCInst TmpInst;
 312     MCInstLowering.lower(MI, TmpInst);
 313     EmitToStreamer(*OutStreamer, TmpInst);
 314
 315 #ifdef EXPENSIVE_CHECKS
 316     // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
 317     // work correctly for the generic CPU).
 318     //
 319     // The isPseudo check really shouldn't be here, but unfortunately there are
 320     // some negative lit tests that depend on being able to continue through
 321     // here even when pseudo instructions haven't been lowered.
 322     if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU())) {
 323       SmallVector<MCFixup, 4> Fixups;
 324       SmallVector<char, 16> CodeBytes;
 325       raw_svector_ostream CodeStream(CodeBytes);
 326
 327       std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
 328           *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
 329       InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
 330
 331       assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
 332     }
 333 #endif
 334
 335     if (DumpCodeInstEmitter) {
 336       // Disassemble instruction/operands to text
 337       DisasmLines.resize(DisasmLines.size() + 1);
 338       std::string &DisasmLine = DisasmLines.back();
 339       raw_string_ostream DisasmStream(DisasmLine);
 340
 341       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
 342                                     *STI.getRegisterInfo());
 343       InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
 344
 345       // Disassemble instruction/operands to hex representation.
 346       SmallVector<MCFixup, 4> Fixups;
 347       SmallVector<char, 16> CodeBytes;
 348       raw_svector_ostream CodeStream(CodeBytes);
 349
 350       DumpCodeInstEmitter->encodeInstruction(
 351           TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
 352       HexLines.resize(HexLines.size() + 1);
 353       std::string &HexLine = HexLines.back();
 354       raw_string_ostream HexStream(HexLine);
 355
 356       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
 357         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
 358         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
 359       }
 360
 361       DisasmStream.flush();
 362       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
 363     }
 364   }
 365 }
 366
 367 R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
 368                                  const AsmPrinter &AP) :
 369         AMDGPUMCInstLower(Ctx, ST, AP) { }
 370
 371 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
 372   OutMI.setOpcode(MI->getOpcode());
 373   for (const MachineOperand &MO : MI->explicit_operands()) {
 374     MCOperand MCOp;
 375     lowerOperand(MO, MCOp);
 376     OutMI.addOperand(MCOp);
 377   }
 378 }
 379
 380 void R600AsmPrinter::EmitInstruction(const MachineInstr *MI) {
 381   const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
 382   R600MCInstLower MCInstLowering(OutContext, STI, *this);
 383
 384   StringRef Err;
 385   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
 386     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
 387     C.emitError("Illegal instruction detected: " + Err);
 388     MI->print(errs());
 389   }
 390
 391   if (MI->isBundle()) {
 392     const MachineBasicBlock *MBB = MI->getParent();
 393     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
 394     while (I != MBB->instr_end() && I->isInsideBundle()) {
 395       EmitInstruction(&*I);
 396       ++I;
 397     }
 398   } else {
 399     MCInst TmpInst;
 400     MCInstLowering.lower(MI, TmpInst);
 401     EmitToStreamer(*OutStreamer, TmpInst);
 402  }
 403 }
 404
 405 const MCExpr *R600AsmPrinter::lowerConstant(const Constant *CV) {
 406   if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
 407     return E;
 408   return AsmPrinter::lowerConstant(CV);
 409 }