lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

   1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  15
  16 #include "llvm/CodeGen/Register.h"
  17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  18
  19 #define GET_REGBANK_DECLARATIONS
  20 #include "AMDGPUGenRegisterBank.inc"
  21 #undef GET_REGBANK_DECLARATIONS
  22
  23 namespace llvm {
  24
  25 class LLT;
  26 class GCNSubtarget;
  27 class MachineIRBuilder;
  28 class SIInstrInfo;
  29 class SIRegisterInfo;
  30 class TargetRegisterInfo;
  31
  32 /// This class provides the information for the target register banks.
  33 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
  34
  35 protected:
  36
  37 #define GET_TARGET_REGBANK_CLASS
  38 #include "AMDGPUGenRegisterBank.inc"
  39 };
  40 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
  41   const GCNSubtarget &Subtarget;
  42   const SIRegisterInfo *TRI;
  43   const SIInstrInfo *TII;
  44
  45   bool executeInWaterfallLoop(MachineIRBuilder &B,
  46                               MachineInstr &MI,
  47                               MachineRegisterInfo &MRI,
  48                               ArrayRef<unsigned> OpIndices) const;
  49   bool executeInWaterfallLoop(MachineInstr &MI,
  50                               MachineRegisterInfo &MRI,
  51                               ArrayRef<unsigned> OpIndices) const;
  52
  53   void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
  54                                     unsigned OpIdx) const;
  55   bool applyMappingWideLoad(MachineInstr &MI,
  56                             const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
  57                             MachineRegisterInfo &MRI) const;
  58   bool
  59   applyMappingImage(MachineInstr &MI,
  60                     const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
  61                     MachineRegisterInfo &MRI, int RSrcIdx) const;
  62
  63   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
  64                           Register Reg) const;
  65
  66   std::pair<Register, unsigned>
  67   splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
  68
  69   MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
  70                                      MachineInstr &MI) const;
  71
  72   /// See RegisterBankInfo::applyMapping.
  73   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
  74
  75   const RegisterBankInfo::InstructionMapping &
  76   getInstrMappingForLoad(const MachineInstr &MI) const;
  77
  78   unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
  79                         const TargetRegisterInfo &TRI,
  80                         unsigned Default = AMDGPU::VGPRRegBankID) const;
  81
  82   // Return a value mapping for an operand that is required to be an SGPR.
  83   const ValueMapping *getSGPROpMapping(Register Reg,
  84                                        const MachineRegisterInfo &MRI,
  85                                        const TargetRegisterInfo &TRI) const;
  86
  87   // Return a value mapping for an operand that is required to be a VGPR.
  88   const ValueMapping *getVGPROpMapping(Register Reg,
  89                                        const MachineRegisterInfo &MRI,
  90                                        const TargetRegisterInfo &TRI) const;
  91
  92   /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
  93   /// Regs. This appropriately sets the regbank of the new registers.
  94   void split64BitValueForMapping(MachineIRBuilder &B,
  95                                  SmallVector<Register, 2> &Regs,
  96                                  LLT HalfTy,
  97                                  Register Reg) const;
  98
  99   template <unsigned NumOps>
 100   struct OpRegBankEntry {
 101     int8_t RegBanks[NumOps];
 102     int16_t Cost;
 103   };
 104
 105   template <unsigned NumOps>
 106   InstructionMappings
 107   addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
 108                       const std::array<unsigned, NumOps> RegSrcOpIdx,
 109                       ArrayRef<OpRegBankEntry<NumOps>> Table) const;
 110
 111   RegisterBankInfo::InstructionMappings
 112   getInstrAlternativeMappingsIntrinsic(
 113       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 114
 115   RegisterBankInfo::InstructionMappings
 116   getInstrAlternativeMappingsIntrinsicWSideEffects(
 117       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 118
 119   bool isSALUMapping(const MachineInstr &MI) const;
 120   const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
 121   const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
 122   const InstructionMapping &getDefaultMappingAllVGPR(
 123     const MachineInstr &MI) const;
 124
 125   const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
 126                                             const MachineInstr &MI,
 127                                             int RsrcIdx) const;
 128
 129 public:
 130   AMDGPURegisterBankInfo(const GCNSubtarget &STI);
 131
 132   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
 133                     unsigned Size) const override;
 134
 135   unsigned getBreakDownCost(const ValueMapping &ValMapping,
 136                             const RegisterBank *CurBank = nullptr) const override;
 137
 138   const RegisterBank &
 139   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 140
 141   InstructionMappings
 142   getInstrAlternativeMappings(const MachineInstr &MI) const override;
 143
 144   const InstructionMapping &
 145   getInstrMapping(const MachineInstr &MI) const override;
 146 };
 147 } // End llvm namespace.
 148 #endif