lib/Target/AMDGPU/AMDGPURegisterInfo.cpp

   1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Parent TargetRegisterInfo class common to all hw codegen targets.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPURegisterInfo.h"
  15 #include "AMDGPUTargetMachine.h"
  16 #include "SIMachineFunctionInfo.h"
  17 #include "SIRegisterInfo.h"
  18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  19
  20 using namespace llvm;
  21
  22 AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
  23
  24 //===----------------------------------------------------------------------===//
  25 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
  26 // they are not supported at this time.
  27 //===----------------------------------------------------------------------===//
  28
  29 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
  30   static const unsigned SubRegs[] = {
  31     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
  32     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
  33     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
  34     AMDGPU::sub15, AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
  35     AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23, AMDGPU::sub24,
  36     AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27, AMDGPU::sub28, AMDGPU::sub29,
  37     AMDGPU::sub30, AMDGPU::sub31
  38   };
  39
  40   assert(Channel < array_lengthof(SubRegs));
  41   return SubRegs[Channel];
  42 }
  43
  44 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
  45   MCRegAliasIterator R(Reg, this, true);
  46
  47   for (; R.isValid(); ++R)
  48     Reserved.set(*R);
  49 }
  50
  51 #define GET_REGINFO_TARGET_DESC
  52 #include "AMDGPUGenRegisterInfo.inc"
  53
  54 // Forced to be here by one .inc
  55 const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
  56   const MachineFunction *MF) const {
  57   CallingConv::ID CC = MF->getFunction().getCallingConv();
  58   switch (CC) {
  59   case CallingConv::C:
  60   case CallingConv::Fast:
  61   case CallingConv::Cold:
  62     return CSR_AMDGPU_HighRegs_SaveList;
  63   default: {
  64     // Dummy to not crash RegisterClassInfo.
  65     static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
  66     return &NoCalleeSavedReg;
  67   }
  68   }
  69 }
  70
  71 const MCPhysReg *
  72 SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
  73   return nullptr;
  74 }
  75
  76 const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
  77                                                      CallingConv::ID CC) const {
  78   switch (CC) {
  79   case CallingConv::C:
  80   case CallingConv::Fast:
  81   case CallingConv::Cold:
  82     return CSR_AMDGPU_HighRegs_RegMask;
  83   default:
  84     return nullptr;
  85   }
  86 }
  87
  88 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
  89   const SIFrameLowering *TFI =
  90       MF.getSubtarget<GCNSubtarget>().getFrameLowering();
  91   const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
  92   return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
  93                         : FuncInfo->getStackPtrOffsetReg();
  94 }
  95
  96 const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const {
  97   return CSR_AMDGPU_AllVGPRs_RegMask;
  98 }
  99
 100 const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const {
 101   return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
 102 }