lib/Target/AMDGPU/GCNHazardRecognizer.h

   1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines hazard recognizers for scheduling on GCN processors.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
  14 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
  15
  16 #include "llvm/ADT/BitVector.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
  19 #include "llvm/CodeGen/TargetSchedule.h"
  20 #include <list>
  21
  22 namespace llvm {
  23
  24 class MachineFunction;
  25 class MachineInstr;
  26 class MachineOperand;
  27 class MachineRegisterInfo;
  28 class ScheduleDAG;
  29 class SIInstrInfo;
  30 class SIRegisterInfo;
  31 class GCNSubtarget;
  32
  33 class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
  34 public:
  35   typedef function_ref<bool(MachineInstr *)> IsHazardFn;
  36
  37 private:
  38   // Distinguish if we are called from scheduler or hazard recognizer
  39   bool IsHazardRecognizerMode;
  40
  41   // This variable stores the instruction that has been emitted this cycle. It
  42   // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
  43   // called.
  44   MachineInstr *CurrCycleInstr;
  45   std::list<MachineInstr*> EmittedInstrs;
  46   const MachineFunction &MF;
  47   const GCNSubtarget &ST;
  48   const SIInstrInfo &TII;
  49   const SIRegisterInfo &TRI;
  50   TargetSchedModel TSchedModel;
  51
  52   /// RegUnits of uses in the current soft memory clause.
  53   BitVector ClauseUses;
  54
  55   /// RegUnits of defs in the current soft memory clause.
  56   BitVector ClauseDefs;
  57
  58   void resetClause() {
  59     ClauseUses.reset();
  60     ClauseDefs.reset();
  61   }
  62
  63   void addClauseInst(const MachineInstr &MI);
  64
  65   // Advance over a MachineInstr bundle. Look for hazards in the bundled
  66   // instructions.
  67   void processBundle();
  68
  69   int getWaitStatesSince(IsHazardFn IsHazard, int Limit);
  70   int getWaitStatesSinceDef(unsigned Reg, IsHazardFn IsHazardDef, int Limit);
  71   int getWaitStatesSinceSetReg(IsHazardFn IsHazard, int Limit);
  72
  73   int checkSoftClauseHazards(MachineInstr *SMEM);
  74   int checkSMRDHazards(MachineInstr *SMRD);
  75   int checkVMEMHazards(MachineInstr* VMEM);
  76   int checkDPPHazards(MachineInstr *DPP);
  77   int checkDivFMasHazards(MachineInstr *DivFMas);
  78   int checkGetRegHazards(MachineInstr *GetRegInstr);
  79   int checkSetRegHazards(MachineInstr *SetRegInstr);
  80   int createsVALUHazard(const MachineInstr &MI);
  81   int checkVALUHazards(MachineInstr *VALU);
  82   int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
  83   int checkRWLaneHazards(MachineInstr *RWLane);
  84   int checkRFEHazards(MachineInstr *RFE);
  85   int checkInlineAsmHazards(MachineInstr *IA);
  86   int checkAnyInstHazards(MachineInstr *MI);
  87   int checkReadM0Hazards(MachineInstr *SMovRel);
  88   int checkNSAtoVMEMHazard(MachineInstr *MI);
  89   int checkFPAtomicToDenormModeHazard(MachineInstr *MI);
  90   void fixHazards(MachineInstr *MI);
  91   bool fixVcmpxPermlaneHazards(MachineInstr *MI);
  92   bool fixVMEMtoScalarWriteHazards(MachineInstr *MI);
  93   bool fixSMEMtoVectorWriteHazards(MachineInstr *MI);
  94   bool fixVcmpxExecWARHazard(MachineInstr *MI);
  95   bool fixLdsBranchVmemWARHazard(MachineInstr *MI);
  96
  97   int checkMAIHazards(MachineInstr *MI);
  98   int checkMAILdStHazards(MachineInstr *MI);
  99
 100 public:
 101   GCNHazardRecognizer(const MachineFunction &MF);
 102   // We can only issue one instruction per cycle.
 103   bool atIssueLimit() const override { return true; }
 104   void EmitInstruction(SUnit *SU) override;
 105   void EmitInstruction(MachineInstr *MI) override;
 106   HazardType getHazardType(SUnit *SU, int Stalls) override;
 107   void EmitNoop() override;
 108   unsigned PreEmitNoops(SUnit *SU) override;
 109   unsigned PreEmitNoops(MachineInstr *) override;
 110   unsigned PreEmitNoopsCommon(MachineInstr *);
 111   void AdvanceCycle() override;
 112   void RecedeCycle() override;
 113 };
 114
 115 } // end namespace llvm
 116
 117 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H