lib/Target/AMDGPU/R600InstrInfo.h

   1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Interface definition for R600InstrInfo
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
  15 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
  16
  17 #include "R600RegisterInfo.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19
  20 #define GET_INSTRINFO_HEADER
  21 #include "R600GenInstrInfo.inc"
  22
  23 namespace llvm {
  24
  25 namespace R600InstrFlags {
  26 enum : uint64_t {
  27  REGISTER_STORE = UINT64_C(1) << 62,
  28  REGISTER_LOAD = UINT64_C(1) << 63
  29 };
  30 }
  31
  32 class AMDGPUTargetMachine;
  33 class DFAPacketizer;
  34 class MachineFunction;
  35 class MachineInstr;
  36 class MachineInstrBuilder;
  37 class R600Subtarget;
  38
  39 class R600InstrInfo final : public R600GenInstrInfo {
  40 private:
  41   const R600RegisterInfo RI;
  42   const R600Subtarget &ST;
  43
  44   std::vector<std::pair<int, unsigned>>
  45   ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
  46               unsigned &ConstCount) const;
  47
  48   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
  49                                         MachineBasicBlock::iterator I,
  50                                         unsigned ValueReg, unsigned Address,
  51                                         unsigned OffsetReg,
  52                                         unsigned AddrChan) const;
  53
  54   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
  55                                          MachineBasicBlock::iterator I,
  56                                          unsigned ValueReg, unsigned Address,
  57                                          unsigned OffsetReg,
  58                                          unsigned AddrChan) const;
  59 public:
  60   enum BankSwizzle {
  61     ALU_VEC_012_SCL_210 = 0,
  62     ALU_VEC_021_SCL_122,
  63     ALU_VEC_120_SCL_212,
  64     ALU_VEC_102_SCL_221,
  65     ALU_VEC_201,
  66     ALU_VEC_210
  67   };
  68
  69   explicit R600InstrInfo(const R600Subtarget &);
  70
  71   const R600RegisterInfo &getRegisterInfo() const {
  72     return RI;
  73   }
  74
  75   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  76                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
  77                    bool KillSrc) const override;
  78   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  79                            MachineBasicBlock::iterator MBBI) const override;
  80
  81   bool isReductionOp(unsigned opcode) const;
  82   bool isCubeOp(unsigned opcode) const;
  83
  84   /// \returns true if this \p Opcode represents an ALU instruction.
  85   bool isALUInstr(unsigned Opcode) const;
  86   bool hasInstrModifiers(unsigned Opcode) const;
  87   bool isLDSInstr(unsigned Opcode) const;
  88   bool isLDSRetInstr(unsigned Opcode) const;
  89
  90   /// \returns true if this \p Opcode represents an ALU instruction or an
  91   /// instruction that will be lowered in ExpandSpecialInstrs Pass.
  92   bool canBeConsideredALU(const MachineInstr &MI) const;
  93
  94   bool isTransOnly(unsigned Opcode) const;
  95   bool isTransOnly(const MachineInstr &MI) const;
  96   bool isVectorOnly(unsigned Opcode) const;
  97   bool isVectorOnly(const MachineInstr &MI) const;
  98   bool isExport(unsigned Opcode) const;
  99
 100   bool usesVertexCache(unsigned Opcode) const;
 101   bool usesVertexCache(const MachineInstr &MI) const;
 102   bool usesTextureCache(unsigned Opcode) const;
 103   bool usesTextureCache(const MachineInstr &MI) const;
 104
 105   bool mustBeLastInClause(unsigned Opcode) const;
 106   bool usesAddressRegister(MachineInstr &MI) const;
 107   bool definesAddressRegister(MachineInstr &MI) const;
 108   bool readsLDSSrcReg(const MachineInstr &MI) const;
 109
 110   /// \returns The operand Index for the Sel operand given an index to one
 111   /// of the instruction's src operands.
 112   int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
 113
 114   /// \returns a pair for each src of an ALU instructions.
 115   /// The first member of a pair is the register id.
 116   /// If register is ALU_CONST, second member is SEL.
 117   /// If register is ALU_LITERAL, second member is IMM.
 118   /// Otherwise, second member value is undefined.
 119   SmallVector<std::pair<MachineOperand *, int64_t>, 3>
 120   getSrcs(MachineInstr &MI) const;
 121
 122   unsigned  isLegalUpTo(
 123     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
 124     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
 125     const std::vector<std::pair<int, unsigned> > &TransSrcs,
 126     R600InstrInfo::BankSwizzle TransSwz) const;
 127
 128   bool FindSwizzleForVectorSlot(
 129     const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
 130     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
 131     const std::vector<std::pair<int, unsigned> > &TransSrcs,
 132     R600InstrInfo::BankSwizzle TransSwz) const;
 133
 134   /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
 135   /// returns true and the first (in lexical order) BankSwizzle affectation
 136   /// starting from the one already provided in the Instruction Group MIs that
 137   /// fits Read Port limitations in BS if available. Otherwise returns false
 138   /// and undefined content in BS.
 139   /// isLastAluTrans should be set if the last Alu of MIs will be executed on
 140   /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
 141   /// apply to the last instruction.
 142   /// PV holds GPR to PV registers in the Instruction Group MIs.
 143   bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
 144                                const DenseMap<unsigned, unsigned> &PV,
 145                                std::vector<BankSwizzle> &BS,
 146                                bool isLastAluTrans) const;
 147
 148   /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
 149   /// from KCache bank on R700+. This function check if MI set in input meet
 150   /// this limitations
 151   bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
 152   /// Same but using const index set instead of MI set.
 153   bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
 154
 155   /// Vector instructions are instructions that must fill all
 156   /// instruction slots within an instruction group.
 157   bool isVector(const MachineInstr &MI) const;
 158
 159   bool isMov(unsigned Opcode) const;
 160
 161   DFAPacketizer *
 162   CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
 163
 164   bool reverseBranchCondition(
 165     SmallVectorImpl<MachineOperand> &Cond) const override;
 166
 167   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 168                      MachineBasicBlock *&FBB,
 169                      SmallVectorImpl<MachineOperand> &Cond,
 170                      bool AllowModify) const override;
 171
 172   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 173                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
 174                         const DebugLoc &DL,
 175                         int *BytesAdded = nullptr) const override;
 176
 177   unsigned removeBranch(MachineBasicBlock &MBB,
 178                         int *BytesRemvoed = nullptr) const override;
 179
 180   bool isPredicated(const MachineInstr &MI) const override;
 181
 182   bool isPredicable(const MachineInstr &MI) const override;
 183
 184   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 185                                  BranchProbability Probability) const override;
 186
 187   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 188                            unsigned ExtraPredCycles,
 189                            BranchProbability Probability) const override ;
 190
 191   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 192                            unsigned NumTCycles, unsigned ExtraTCycles,
 193                            MachineBasicBlock &FMBB,
 194                            unsigned NumFCycles, unsigned ExtraFCycles,
 195                            BranchProbability Probability) const override;
 196
 197   bool DefinesPredicate(MachineInstr &MI,
 198                         std::vector<MachineOperand> &Pred) const override;
 199
 200   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
 201                                  MachineBasicBlock &FMBB) const override;
 202
 203   bool PredicateInstruction(MachineInstr &MI,
 204                             ArrayRef<MachineOperand> Pred) const override;
 205
 206   unsigned int getPredicationCost(const MachineInstr &) const override;
 207
 208   unsigned int getInstrLatency(const InstrItineraryData *ItinData,
 209                                const MachineInstr &MI,
 210                                unsigned *PredCost = nullptr) const override;
 211
 212   bool expandPostRAPseudo(MachineInstr &MI) const override;
 213
 214   /// Reserve the registers that may be accesed using indirect addressing.
 215   void reserveIndirectRegisters(BitVector &Reserved,
 216                                 const MachineFunction &MF,
 217                                 const R600RegisterInfo &TRI) const;
 218
 219   /// Calculate the "Indirect Address" for the given \p RegIndex and
 220   /// \p Channel
 221   ///
 222   /// We model indirect addressing using a virtual address space that can be
 223   /// accesed with loads and stores.  The "Indirect Address" is the memory
 224   /// address in this virtual address space that maps to the given \p RegIndex
 225   /// and \p Channel.
 226   unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
 227
 228
 229   /// \returns The register class to be used for loading and storing values
 230   /// from an "Indirect Address" .
 231   const TargetRegisterClass *getIndirectAddrRegClass() const;
 232
 233   /// \returns the smallest register index that will be accessed by an indirect
 234   /// read or write or -1 if indirect addressing is not used by this program.
 235   int getIndirectIndexBegin(const MachineFunction &MF) const;
 236
 237   /// \returns the largest register index that will be accessed by an indirect
 238   /// read or write or -1 if indirect addressing is not used by this program.
 239   int getIndirectIndexEnd(const MachineFunction &MF) const;
 240
 241   /// Build instruction(s) for an indirect register write.
 242   ///
 243   /// \returns The instruction that performs the indirect register write
 244   MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
 245                                          MachineBasicBlock::iterator I,
 246                                          unsigned ValueReg, unsigned Address,
 247                                          unsigned OffsetReg) const;
 248
 249   /// Build instruction(s) for an indirect register read.
 250   ///
 251   /// \returns The instruction that performs the indirect register read
 252   MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
 253                                         MachineBasicBlock::iterator I,
 254                                         unsigned ValueReg, unsigned Address,
 255                                         unsigned OffsetReg) const;
 256
 257   unsigned getMaxAlusPerClause() const;
 258
 259   /// buildDefaultInstruction - This function returns a MachineInstr with all
 260   /// the instruction modifiers initialized to their default values.  You can
 261   /// use this function to avoid manually specifying each instruction modifier
 262   /// operand when building a new instruction.
 263   ///
 264   /// \returns a MachineInstr with all the instruction modifiers initialized
 265   /// to their default values.
 266   MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
 267                                               MachineBasicBlock::iterator I,
 268                                               unsigned Opcode,
 269                                               unsigned DstReg,
 270                                               unsigned Src0Reg,
 271                                               unsigned Src1Reg = 0) const;
 272
 273   MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
 274                                              MachineInstr *MI,
 275                                              unsigned Slot,
 276                                              unsigned DstReg) const;
 277
 278   MachineInstr *buildMovImm(MachineBasicBlock &BB,
 279                             MachineBasicBlock::iterator I,
 280                             unsigned DstReg,
 281                             uint64_t Imm) const;
 282
 283   MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
 284                               MachineBasicBlock::iterator I,
 285                               unsigned DstReg, unsigned SrcReg) const;
 286
 287   /// Get the index of Op in the MachineInstr.
 288   ///
 289   /// \returns -1 if the Instruction does not contain the specified \p Op.
 290   int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
 291
 292   /// Get the index of \p Op for the given Opcode.
 293   ///
 294   /// \returns -1 if the Instruction does not contain the specified \p Op.
 295   int getOperandIdx(unsigned Opcode, unsigned Op) const;
 296
 297   /// Helper function for setting instruction flag values.
 298   void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
 299
 300   ///Add one of the MO_FLAG* flags to the specified \p Operand.
 301   void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
 302
 303   ///Determine if the specified \p Flag is set on this \p Operand.
 304   bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
 305
 306   /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
 307   /// \param Flag The flag being set.
 308   ///
 309   /// \returns the operand containing the flags for this instruction.
 310   MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
 311                             unsigned Flag = 0) const;
 312
 313   /// Clear the specified flag on the instruction.
 314   void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
 315
 316   // Helper functions that check the opcode for status information
 317   bool isRegisterStore(const MachineInstr &MI) const {
 318     return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
 319   }
 320
 321   bool isRegisterLoad(const MachineInstr &MI) const {
 322     return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
 323   }
 324
 325   unsigned getAddressSpaceForPseudoSourceKind(
 326       unsigned Kind) const override;
 327 };
 328
 329 namespace R600 {
 330
 331 int getLDSNoRetOp(uint16_t Opcode);
 332
 333 } //End namespace AMDGPU
 334
 335 } // End llvm namespace
 336
 337 #endif