lib/Target/AMDGPU/R600RegisterInfo.h

   1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Interface definition for R600RegisterInfo
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
  15 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
  16
  17 #define GET_REGINFO_HEADER
  18 #include "R600GenRegisterInfo.inc"
  19
  20 namespace llvm {
  21
  22 struct R600RegisterInfo final : public R600GenRegisterInfo {
  23   RegClassWeight RCW;
  24
  25   R600RegisterInfo();
  26
  27   BitVector getReservedRegs(const MachineFunction &MF) const override;
  28   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  29   Register getFrameRegister(const MachineFunction &MF) const override;
  30
  31   /// get the HW encoding for a register's channel.
  32   unsigned getHWRegChan(unsigned reg) const;
  33
  34   unsigned getHWRegIndex(unsigned Reg) const;
  35
  36   /// get the register class of the specified type to use in the
  37   /// CFGStructurizer
  38   const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
  39
  40   const RegClassWeight &
  41     getRegClassWeight(const TargetRegisterClass *RC) const override;
  42
  43   // \returns true if \p Reg can be defined in one ALU clause and used in
  44   // another.
  45   bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
  46
  47   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
  48                            unsigned FIOperandNum,
  49                            RegScavenger *RS = nullptr) const override;
  50
  51   void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
  52 };
  53
  54 } // End namespace llvm
  55
  56 #endif