lib/Target/AMDGPU/SIFixVGPRCopies.cpp

   1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Add implicit use of exec to vector register copies.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AMDGPU.h"
  15 #include "AMDGPUSubtarget.h"
  16 #include "SIInstrInfo.h"
  17 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  18 #include "llvm/CodeGen/MachineFunctionPass.h"
  19
  20 using namespace llvm;
  21
  22 #define DEBUG_TYPE "si-fix-vgpr-copies"
  23
  24 namespace {
  25
  26 class SIFixVGPRCopies : public MachineFunctionPass {
  27 public:
  28   static char ID;
  29
  30 public:
  31   SIFixVGPRCopies() : MachineFunctionPass(ID) {
  32     initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
  33   }
  34
  35   bool runOnMachineFunction(MachineFunction &MF) override;
  36
  37   StringRef getPassName() const override { return "SI Fix VGPR copies"; }
  38 };
  39
  40 } // End anonymous namespace.
  41
  42 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
  43
  44 char SIFixVGPRCopies::ID = 0;
  45
  46 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
  47
  48 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
  49   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
  50   const SIRegisterInfo *TRI = ST.getRegisterInfo();
  51   const SIInstrInfo *TII = ST.getInstrInfo();
  52   bool Changed = false;
  53
  54   for (MachineBasicBlock &MBB : MF) {
  55     for (MachineInstr &MI : MBB) {
  56       switch (MI.getOpcode()) {
  57       case AMDGPU::COPY:
  58         if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
  59           MI.addOperand(MF,
  60                         MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
  61           LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
  62           Changed = true;
  63         }
  64         break;
  65       default:
  66         break;
  67       }
  68     }
  69   }
  70
  71   return Changed;
  72 }