lib/Target/PowerPC/PPCSubtarget.cpp

   1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "PPCSubtarget.h"
  14 #include "PPC.h"
  15 #include "PPCRegisterInfo.h"
  16 #include "PPCTargetMachine.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/MachineScheduler.h"
  19 #include "llvm/IR/Attributes.h"
  20 #include "llvm/IR/Function.h"
  21 #include "llvm/IR/GlobalValue.h"
  22 #include "llvm/Support/CommandLine.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24 #include "llvm/Target/TargetMachine.h"
  25 #include <cstdlib>
  26
  27 using namespace llvm;
  28
  29 #define DEBUG_TYPE "ppc-subtarget"
  30
  31 #define GET_SUBTARGETINFO_TARGET_DESC
  32 #define GET_SUBTARGETINFO_CTOR
  33 #include "PPCGenSubtargetInfo.inc"
  34
  35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
  36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
  37
  38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
  39   cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
  40   cl::Hidden);
  41
  42 static cl::opt<bool>
  43     EnableMachinePipeliner("ppc-enable-pipeliner",
  44                            cl::desc("Enable Machine Pipeliner for PPC"),
  45                            cl::init(false), cl::Hidden);
  46
  47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
  48                                                             StringRef FS) {
  49   initializeEnvironment();
  50   initSubtargetFeatures(CPU, FS);
  51   return *this;
  52 }
  53
  54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
  55                            const std::string &FS, const PPCTargetMachine &TM)
  56     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
  57       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
  58               TargetTriple.getArch() == Triple::ppc64le),
  59       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
  60       InstrInfo(*this), TLInfo(TM, *this) {}
  61
  62 void PPCSubtarget::initializeEnvironment() {
  63   StackAlignment = 16;
  64   DarwinDirective = PPC::DIR_NONE;
  65   HasMFOCRF = false;
  66   Has64BitSupport = false;
  67   Use64BitRegs = false;
  68   UseCRBits = false;
  69   HasHardFloat = false;
  70   HasAltivec = false;
  71   HasSPE = false;
  72   HasFPU = false;
  73   HasQPX = false;
  74   HasVSX = false;
  75   NeedsTwoConstNR = false;
  76   HasP8Vector = false;
  77   HasP8Altivec = false;
  78   HasP8Crypto = false;
  79   HasP9Vector = false;
  80   HasP9Altivec = false;
  81   HasFCPSGN = false;
  82   HasFSQRT = false;
  83   HasFRE = false;
  84   HasFRES = false;
  85   HasFRSQRTE = false;
  86   HasFRSQRTES = false;
  87   HasRecipPrec = false;
  88   HasSTFIWX = false;
  89   HasLFIWAX = false;
  90   HasFPRND = false;
  91   HasFPCVT = false;
  92   HasISEL = false;
  93   HasBPERMD = false;
  94   HasExtDiv = false;
  95   HasCMPB = false;
  96   HasLDBRX = false;
  97   IsBookE = false;
  98   HasOnlyMSYNC = false;
  99   IsPPC4xx = false;
 100   IsPPC6xx = false;
 101   IsE500 = false;
 102   FeatureMFTB = false;
 103   DeprecatedDST = false;
 104   HasLazyResolverStubs = false;
 105   HasICBT = false;
 106   HasInvariantFunctionDescriptors = false;
 107   HasPartwordAtomics = false;
 108   HasDirectMove = false;
 109   IsQPXStackUnaligned = false;
 110   HasHTM = false;
 111   HasFloat128 = false;
 112   IsISA3_0 = false;
 113   UseLongCalls = false;
 114   SecurePlt = false;
 115   VectorsUseTwoUnits = false;
 116   UsePPCPreRASchedStrategy = false;
 117   UsePPCPostRASchedStrategy = false;
 118
 119   HasPOPCNTD = POPCNTD_Unavailable;
 120 }
 121
 122 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 123   // Determine default and user specified characteristics
 124   std::string CPUName = CPU;
 125   if (CPUName.empty() || CPU == "generic") {
 126     // If cross-compiling with -march=ppc64le without -mcpu
 127     if (TargetTriple.getArch() == Triple::ppc64le)
 128       CPUName = "ppc64le";
 129     else
 130       CPUName = "generic";
 131   }
 132
 133   // Initialize scheduling itinerary for the specified CPU.
 134   InstrItins = getInstrItineraryForCPU(CPUName);
 135
 136   // Parse features string.
 137   ParseSubtargetFeatures(CPUName, FS);
 138
 139   // If the user requested use of 64-bit regs, but the cpu selected doesn't
 140   // support it, ignore.
 141   if (IsPPC64 && has64BitSupport())
 142     Use64BitRegs = true;
 143
 144   // Set up darwin-specific properties.
 145   if (isDarwin())
 146     HasLazyResolverStubs = true;
 147
 148   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
 149       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
 150       TargetTriple.isMusl())
 151     SecurePlt = true;
 152
 153   if (HasSPE && IsPPC64)
 154     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
 155   if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
 156     report_fatal_error(
 157         "SPE and traditional floating point cannot both be enabled.\n", false);
 158
 159   // If not SPE, set standard FPU
 160   if (!HasSPE)
 161     HasFPU = true;
 162
 163   // QPX requires a 32-byte aligned stack. Note that we need to do this if
 164   // we're compiling for a BG/Q system regardless of whether or not QPX
 165   // is enabled because external functions will assume this alignment.
 166   IsQPXStackUnaligned = QPXStackUnaligned;
 167   StackAlignment = getPlatformStackAlignment();
 168
 169   // Determine endianness.
 170   // FIXME: Part of the TargetMachine.
 171   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
 172 }
 173
 174 /// Return true if accesses to the specified global have to go through a dyld
 175 /// lazy resolution stub.  This means that an extra load is required to get the
 176 /// address of the global.
 177 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
 178   if (!HasLazyResolverStubs)
 179     return false;
 180   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
 181     return true;
 182   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
 183   // the section that is being relocated. This means we have to use o load even
 184   // for GVs that are known to be local to the dso.
 185   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
 186     return true;
 187   return false;
 188 }
 189
 190 bool PPCSubtarget::enableMachineScheduler() const { return true; }
 191
 192 bool PPCSubtarget::enableMachinePipeliner() const {
 193   return (DarwinDirective == PPC::DIR_PWR9) && EnableMachinePipeliner;
 194 }
 195
 196 bool PPCSubtarget::useDFAforSMS() const { return false; }
 197
 198 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
 199 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
 200
 201 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
 202   return TargetSubtargetInfo::ANTIDEP_ALL;
 203 }
 204
 205 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
 206   CriticalPathRCs.clear();
 207   CriticalPathRCs.push_back(isPPC64() ?
 208                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
 209 }
 210
 211 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
 212                                        unsigned NumRegionInstrs) const {
 213   // The GenericScheduler that we use defaults to scheduling bottom up only.
 214   // We want to schedule from both the top and the bottom and so we set
 215   // OnlyBottomUp to false.
 216   // We want to do bi-directional scheduling since it provides a more balanced
 217   // schedule leading to better performance.
 218   Policy.OnlyBottomUp = false;
 219   // Spilling is generally expensive on all PPC cores, so always enable
 220   // register-pressure tracking.
 221   Policy.ShouldTrackPressure = true;
 222 }
 223
 224 bool PPCSubtarget::useAA() const {
 225   return true;
 226 }
 227
 228 bool PPCSubtarget::enableSubRegLiveness() const {
 229   return UseSubRegLiveness;
 230 }
 231
 232 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
 233   // Large code model always uses the TOC even for local symbols.
 234   if (TM.getCodeModel() == CodeModel::Large)
 235     return true;
 236   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
 237     return false;
 238   return true;
 239 }
 240
 241 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
 242 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }