lib/Target/SystemZ/SystemZShortenInst.cpp

   1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This pass tries to replace instructions with shorter forms.  For example,
  10 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
  11 // other 32 bits of the GR64 destination are not live.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SystemZTargetMachine.h"
  16 #include "llvm/CodeGen/LivePhysRegs.h"
  17 #include "llvm/CodeGen/MachineFunctionPass.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/TargetRegisterInfo.h"
  20
  21 using namespace llvm;
  22
  23 #define DEBUG_TYPE "systemz-shorten-inst"
  24
  25 namespace {
  26 class SystemZShortenInst : public MachineFunctionPass {
  27 public:
  28   static char ID;
  29   SystemZShortenInst(const SystemZTargetMachine &tm);
  30
  31   StringRef getPassName() const override {
  32     return "SystemZ Instruction Shortening";
  33   }
  34
  35   bool processBlock(MachineBasicBlock &MBB);
  36   bool runOnMachineFunction(MachineFunction &F) override;
  37   MachineFunctionProperties getRequiredProperties() const override {
  38     return MachineFunctionProperties().set(
  39         MachineFunctionProperties::Property::NoVRegs);
  40   }
  41
  42 private:
  43   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
  44   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
  45   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
  46   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
  47   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
  48   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
  49   bool shortenSelect(MachineInstr &MI, unsigned Opcode);
  50
  51   const SystemZInstrInfo *TII;
  52   const TargetRegisterInfo *TRI;
  53   LivePhysRegs LiveRegs;
  54 };
  55
  56 char SystemZShortenInst::ID = 0;
  57 } // end anonymous namespace
  58
  59 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
  60   return new SystemZShortenInst(TM);
  61 }
  62
  63 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
  64   : MachineFunctionPass(ID), TII(nullptr) {}
  65
  66 // Tie operands if MI has become a two-address instruction.
  67 static void tieOpsIfNeeded(MachineInstr &MI) {
  68   if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
  69       !MI.getOperand(0).isTied())
  70     MI.tieOperands(0, 1);
  71 }
  72
  73 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
  74 // are the halfword immediate loads for the same word.  Try to use one of them
  75 // instead of IIxF.
  76 bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
  77                                     unsigned LLIxH) {
  78   Register Reg = MI.getOperand(0).getReg();
  79   // The new opcode will clear the other half of the GR64 reg, so
  80   // cancel if that is live.
  81   unsigned thisSubRegIdx =
  82       (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
  83                                                : SystemZ::subreg_l32);
  84   unsigned otherSubRegIdx =
  85       (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
  86                                             : SystemZ::subreg_l32);
  87   unsigned GR64BitReg =
  88       TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
  89   Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
  90   if (LiveRegs.contains(OtherReg))
  91     return false;
  92
  93   uint64_t Imm = MI.getOperand(1).getImm();
  94   if (SystemZ::isImmLL(Imm)) {
  95     MI.setDesc(TII->get(LLIxL));
  96     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
  97     return true;
  98   }
  99   if (SystemZ::isImmLH(Imm)) {
 100     MI.setDesc(TII->get(LLIxH));
 101     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
 102     MI.getOperand(1).setImm(Imm >> 16);
 103     return true;
 104   }
 105   return false;
 106 }
 107
 108 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
 110   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
 111     MI.setDesc(TII->get(Opcode));
 112     return true;
 113   }
 114   return false;
 115 }
 116
 117 // Change MI's opcode to Opcode if register operands 0 and 1 have a
 118 // 4-bit encoding.
 119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
 120   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 121       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
 122     MI.setDesc(TII->get(Opcode));
 123     return true;
 124   }
 125   return false;
 126 }
 127
 128 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
 129 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
 130 // with op 1, if MI becomes 2-address.
 131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
 132   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 133       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
 134       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
 135     MI.setDesc(TII->get(Opcode));
 136     tieOpsIfNeeded(MI);
 137     return true;
 138   }
 139   return false;
 140 }
 141
 142 // Calls shortenOn001 if CCLive is false. CC def operand is added in
 143 // case of success.
 144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
 145   if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
 146     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
 147       .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
 148     return true;
 149   }
 150   return false;
 151 }
 152
 153 // MI is a vector-style conversion instruction with the operand order:
 154 // destination, source, exact-suppress, rounding-mode.  If both registers
 155 // have a 4-bit encoding then change it to Opcode, which has operand order:
 156 // destination, rouding-mode, source, exact-suppress.
 157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
 158   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
 159       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
 160     MachineOperand Dest(MI.getOperand(0));
 161     MachineOperand Src(MI.getOperand(1));
 162     MachineOperand Suppress(MI.getOperand(2));
 163     MachineOperand Mode(MI.getOperand(3));
 164     MI.RemoveOperand(3);
 165     MI.RemoveOperand(2);
 166     MI.RemoveOperand(1);
 167     MI.RemoveOperand(0);
 168     MI.setDesc(TII->get(Opcode));
 169     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
 170         .add(Dest)
 171         .add(Mode)
 172         .add(Src)
 173         .add(Suppress);
 174     return true;
 175   }
 176   return false;
 177 }
 178
 179 // MI is a three-operand select instruction.  If one of the sources match
 180 // the destination, convert to the equivalent load-on-condition.
 181 bool SystemZShortenInst::shortenSelect(MachineInstr &MI, unsigned Opcode) {
 182   if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
 183     MI.setDesc(TII->get(Opcode));
 184     MI.tieOperands(0, 1);
 185     return true;
 186   }
 187   if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
 188     TII->commuteInstruction(MI, false, 1, 2);
 189     MI.setDesc(TII->get(Opcode));
 190     MI.tieOperands(0, 1);
 191     return true;
 192   }
 193   return false;
 194 }
 195
 196 // Process all instructions in MBB.  Return true if something changed.
 197 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
 198   bool Changed = false;
 199
 200   // Set up the set of live registers at the end of MBB (live out)
 201   LiveRegs.clear();
 202   LiveRegs.addLiveOuts(MBB);
 203
 204   // Iterate backwards through the block looking for instructions to change.
 205   for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
 206     MachineInstr &MI = *MBBI;
 207     switch (MI.getOpcode()) {
 208     case SystemZ::IILF:
 209       Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
 210       break;
 211
 212     case SystemZ::IIHF:
 213       Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
 214       break;
 215
 216     case SystemZ::SELR:
 217       Changed |= shortenSelect(MI, SystemZ::LOCR);
 218       break;
 219
 220     case SystemZ::SELFHR:
 221       Changed |= shortenSelect(MI, SystemZ::LOCFHR);
 222       break;
 223
 224     case SystemZ::SELGR:
 225       Changed |= shortenSelect(MI, SystemZ::LOCGR);
 226       break;
 227
 228     case SystemZ::WFADB:
 229       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
 230       break;
 231
 232     case SystemZ::WFASB:
 233       Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);
 234       break;
 235
 236     case SystemZ::WFDDB:
 237       Changed |= shortenOn001(MI, SystemZ::DDBR);
 238       break;
 239
 240     case SystemZ::WFDSB:
 241       Changed |= shortenOn001(MI, SystemZ::DEBR);
 242       break;
 243
 244     case SystemZ::WFIDB:
 245       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
 246       break;
 247
 248     case SystemZ::WFISB:
 249       Changed |= shortenFPConv(MI, SystemZ::FIEBRA);
 250       break;
 251
 252     case SystemZ::WLDEB:
 253       Changed |= shortenOn01(MI, SystemZ::LDEBR);
 254       break;
 255
 256     case SystemZ::WLEDB:
 257       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
 258       break;
 259
 260     case SystemZ::WFMDB:
 261       Changed |= shortenOn001(MI, SystemZ::MDBR);
 262       break;
 263
 264     case SystemZ::WFMSB:
 265       Changed |= shortenOn001(MI, SystemZ::MEEBR);
 266       break;
 267
 268     case SystemZ::WFLCDB:
 269       Changed |= shortenOn01(MI, SystemZ::LCDFR);
 270       break;
 271
 272     case SystemZ::WFLCSB:
 273       Changed |= shortenOn01(MI, SystemZ::LCDFR_32);
 274       break;
 275
 276     case SystemZ::WFLNDB:
 277       Changed |= shortenOn01(MI, SystemZ::LNDFR);
 278       break;
 279
 280     case SystemZ::WFLNSB:
 281       Changed |= shortenOn01(MI, SystemZ::LNDFR_32);
 282       break;
 283
 284     case SystemZ::WFLPDB:
 285       Changed |= shortenOn01(MI, SystemZ::LPDFR);
 286       break;
 287
 288     case SystemZ::WFLPSB:
 289       Changed |= shortenOn01(MI, SystemZ::LPDFR_32);
 290       break;
 291
 292     case SystemZ::WFSQDB:
 293       Changed |= shortenOn01(MI, SystemZ::SQDBR);
 294       break;
 295
 296     case SystemZ::WFSQSB:
 297       Changed |= shortenOn01(MI, SystemZ::SQEBR);
 298       break;
 299
 300     case SystemZ::WFSDB:
 301       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
 302       break;
 303
 304     case SystemZ::WFSSB:
 305       Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);
 306       break;
 307
 308     case SystemZ::WFCDB:
 309       Changed |= shortenOn01(MI, SystemZ::CDBR);
 310       break;
 311
 312     case SystemZ::WFCSB:
 313       Changed |= shortenOn01(MI, SystemZ::CEBR);
 314       break;
 315
 316     case SystemZ::VL32:
 317       // For z13 we prefer LDE over LE to avoid partial register dependencies.
 318       Changed |= shortenOn0(MI, SystemZ::LDE32);
 319       break;
 320
 321     case SystemZ::VST32:
 322       Changed |= shortenOn0(MI, SystemZ::STE);
 323       break;
 324
 325     case SystemZ::VL64:
 326       Changed |= shortenOn0(MI, SystemZ::LD);
 327       break;
 328
 329     case SystemZ::VST64:
 330       Changed |= shortenOn0(MI, SystemZ::STD);
 331       break;
 332
 333     default: {
 334       int TwoOperandOpcode = SystemZ::getTwoOperandOpcode(MI.getOpcode());
 335       if (TwoOperandOpcode == -1)
 336         break;
 337
 338       if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
 339           (!MI.isCommutable() ||
 340            MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
 341            !TII->commuteInstruction(MI, false, 1, 2)))
 342           break;
 343
 344       MI.setDesc(TII->get(TwoOperandOpcode));
 345       MI.tieOperands(0, 1);
 346       if (TwoOperandOpcode == SystemZ::SLL ||
 347           TwoOperandOpcode == SystemZ::SLA ||
 348           TwoOperandOpcode == SystemZ::SRL ||
 349           TwoOperandOpcode == SystemZ::SRA) {
 350         // These shifts only use the low 6 bits of the shift count.
 351         MachineOperand &ImmMO = MI.getOperand(3);
 352         ImmMO.setImm(ImmMO.getImm() & 0xfff);
 353       }
 354       Changed = true;
 355       break;
 356     }
 357     }
 358
 359     LiveRegs.stepBackward(MI);
 360   }
 361
 362   return Changed;
 363 }
 364
 365 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
 366   if (skipFunction(F.getFunction()))
 367     return false;
 368
 369   const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
 370   TII = ST.getInstrInfo();
 371   TRI = ST.getRegisterInfo();
 372   LiveRegs.init(*TRI);
 373
 374   bool Changed = false;
 375   for (auto &MBB : F)
 376     Changed |= processBlock(MBB);
 377
 378   return Changed;
 379 }