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[obj2yaml] - Fix BB after r373315.
[llvm-complete.git] / lib / Target / X86 / X86InstrInfo.cpp
blob7fba03c64252550a41a011e4ec6e5b18c78b84ac
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/DebugInfoMetadata.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42
43 using namespace llvm;
44
45 #define DEBUG_TYPE "x86-instr-info"
46
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49
50 static cl::opt<bool>
51 NoFusing("disable-spill-fusing",
52 cl::desc("Disable fusing of spill code into instructions"),
53 cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56 cl::desc("Print instructions that the allocator wants to"
57 " fuse, but the X86 backend currently can't"),
58 cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61 cl::desc("Re-materialize load from stub in PIC mode"),
62 cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65 cl::desc("Clearance between two register writes "
66 "for inserting XOR to avoid partial "
67 "register update"),
68 cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71 cl::desc("How many idle instructions we would like before "
72 "certain undef register reads"),
73 cl::init(128), cl::Hidden);
74
75
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET,
85 (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86 Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91 unsigned &SrcReg, unsigned &DstReg,
92 unsigned &SubIdx) const {
93 switch (MI.getOpcode()) {
94 default: break;
95 case X86::MOVSX16rr8:
96 case X86::MOVZX16rr8:
97 case X86::MOVSX32rr8:
98 case X86::MOVZX32rr8:
99 case X86::MOVSX64rr8:
100 if (!Subtarget.is64Bit())
101 // It's not always legal to reference the low 8-bit of the larger
102 // register in 32-bit mode.
103 return false;
104 LLVM_FALLTHROUGH;
105 case X86::MOVSX32rr16:
106 case X86::MOVZX32rr16:
107 case X86::MOVSX64rr16:
108 case X86::MOVSX64rr32: {
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110 // Be conservative.
111 return false;
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
114 switch (MI.getOpcode()) {
115 default: llvm_unreachable("Unreachable!");
116 case X86::MOVSX16rr8:
117 case X86::MOVZX16rr8:
118 case X86::MOVSX32rr8:
119 case X86::MOVZX32rr8:
120 case X86::MOVSX64rr8:
121 SubIdx = X86::sub_8bit;
122 break;
123 case X86::MOVSX32rr16:
124 case X86::MOVZX32rr16:
125 case X86::MOVSX64rr16:
126 SubIdx = X86::sub_16bit;
127 break;
128 case X86::MOVSX64rr32:
129 SubIdx = X86::sub_32bit;
130 break;
131 }
132 return true;
133 }
134 }
135 return false;
136 }
137
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139 const MachineFunction *MF = MI.getParent()->getParent();
140 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141
142 if (isFrameInstr(MI)) {
143 unsigned StackAlign = TFI->getStackAlignment();
144 int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145 SPAdj -= getFrameAdjustment(MI);
146 if (!isFrameSetup(MI))
147 SPAdj = -SPAdj;
148 return SPAdj;
149 }
150
151 // To know whether a call adjusts the stack, we need information
152 // that is bound to the following ADJCALLSTACKUP pseudo.
153 // Look for the next ADJCALLSTACKUP that follows the call.
154 if (MI.isCall()) {
155 const MachineBasicBlock *MBB = MI.getParent();
156 auto I = ++MachineBasicBlock::const_iterator(MI);
157 for (auto E = MBB->end(); I != E; ++I) {
158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159 I->isCall())
160 break;
161 }
162
163 // If we could not find a frame destroy opcode, then it has already
164 // been simplified, so we don't care.
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
166 return 0;
167
168 return -(I->getOperand(1).getImm());
169 }
170
171 // Currently handle only PUSHes we can reasonably expect to see
172 // in call sequences
173 switch (MI.getOpcode()) {
174 default:
175 return 0;
176 case X86::PUSH32i8:
177 case X86::PUSH32r:
178 case X86::PUSH32rmm:
179 case X86::PUSH32rmr:
180 case X86::PUSHi32:
181 return 4;
182 case X86::PUSH64i8:
183 case X86::PUSH64r:
184 case X86::PUSH64rmm:
185 case X86::PUSH64rmr:
186 case X86::PUSH64i32:
187 return 8;
188 }
189 }
190
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194 int &FrameIndex) const {
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203 return true;
204 }
205 return false;
206 }
207
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209 switch (Opcode) {
210 default:
211 return false;
212 case X86::MOV8rm:
213 case X86::KMOVBkm:
214 MemBytes = 1;
215 return true;
216 case X86::MOV16rm:
217 case X86::KMOVWkm:
218 MemBytes = 2;
219 return true;
220 case X86::MOV32rm:
221 case X86::MOVSSrm:
222 case X86::MOVSSrm_alt:
223 case X86::VMOVSSrm:
224 case X86::VMOVSSrm_alt:
225 case X86::VMOVSSZrm:
226 case X86::VMOVSSZrm_alt:
227 case X86::KMOVDkm:
228 MemBytes = 4;
229 return true;
230 case X86::MOV64rm:
231 case X86::LD_Fp64m:
232 case X86::MOVSDrm:
233 case X86::MOVSDrm_alt:
234 case X86::VMOVSDrm:
235 case X86::VMOVSDrm_alt:
236 case X86::VMOVSDZrm:
237 case X86::VMOVSDZrm_alt:
238 case X86::MMX_MOVD64rm:
239 case X86::MMX_MOVQ64rm:
240 case X86::KMOVQkm:
241 MemBytes = 8;
242 return true;
243 case X86::MOVAPSrm:
244 case X86::MOVUPSrm:
245 case X86::MOVAPDrm:
246 case X86::MOVUPDrm:
247 case X86::MOVDQArm:
248 case X86::MOVDQUrm:
249 case X86::VMOVAPSrm:
250 case X86::VMOVUPSrm:
251 case X86::VMOVAPDrm:
252 case X86::VMOVUPDrm:
253 case X86::VMOVDQArm:
254 case X86::VMOVDQUrm:
255 case X86::VMOVAPSZ128rm:
256 case X86::VMOVUPSZ128rm:
257 case X86::VMOVAPSZ128rm_NOVLX:
258 case X86::VMOVUPSZ128rm_NOVLX:
259 case X86::VMOVAPDZ128rm:
260 case X86::VMOVUPDZ128rm:
261 case X86::VMOVDQU8Z128rm:
262 case X86::VMOVDQU16Z128rm:
263 case X86::VMOVDQA32Z128rm:
264 case X86::VMOVDQU32Z128rm:
265 case X86::VMOVDQA64Z128rm:
266 case X86::VMOVDQU64Z128rm:
267 MemBytes = 16;
268 return true;
269 case X86::VMOVAPSYrm:
270 case X86::VMOVUPSYrm:
271 case X86::VMOVAPDYrm:
272 case X86::VMOVUPDYrm:
273 case X86::VMOVDQAYrm:
274 case X86::VMOVDQUYrm:
275 case X86::VMOVAPSZ256rm:
276 case X86::VMOVUPSZ256rm:
277 case X86::VMOVAPSZ256rm_NOVLX:
278 case X86::VMOVUPSZ256rm_NOVLX:
279 case X86::VMOVAPDZ256rm:
280 case X86::VMOVUPDZ256rm:
281 case X86::VMOVDQU8Z256rm:
282 case X86::VMOVDQU16Z256rm:
283 case X86::VMOVDQA32Z256rm:
284 case X86::VMOVDQU32Z256rm:
285 case X86::VMOVDQA64Z256rm:
286 case X86::VMOVDQU64Z256rm:
287 MemBytes = 32;
288 return true;
289 case X86::VMOVAPSZrm:
290 case X86::VMOVUPSZrm:
291 case X86::VMOVAPDZrm:
292 case X86::VMOVUPDZrm:
293 case X86::VMOVDQU8Zrm:
294 case X86::VMOVDQU16Zrm:
295 case X86::VMOVDQA32Zrm:
296 case X86::VMOVDQU32Zrm:
297 case X86::VMOVDQA64Zrm:
298 case X86::VMOVDQU64Zrm:
299 MemBytes = 64;
300 return true;
301 }
302 }
303
304 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
305 switch (Opcode) {
306 default:
307 return false;
308 case X86::MOV8mr:
309 case X86::KMOVBmk:
310 MemBytes = 1;
311 return true;
312 case X86::MOV16mr:
313 case X86::KMOVWmk:
314 MemBytes = 2;
315 return true;
316 case X86::MOV32mr:
317 case X86::MOVSSmr:
318 case X86::VMOVSSmr:
319 case X86::VMOVSSZmr:
320 case X86::KMOVDmk:
321 MemBytes = 4;
322 return true;
323 case X86::MOV64mr:
324 case X86::ST_FpP64m:
325 case X86::MOVSDmr:
326 case X86::VMOVSDmr:
327 case X86::VMOVSDZmr:
328 case X86::MMX_MOVD64mr:
329 case X86::MMX_MOVQ64mr:
330 case X86::MMX_MOVNTQmr:
331 case X86::KMOVQmk:
332 MemBytes = 8;
333 return true;
334 case X86::MOVAPSmr:
335 case X86::MOVUPSmr:
336 case X86::MOVAPDmr:
337 case X86::MOVUPDmr:
338 case X86::MOVDQAmr:
339 case X86::MOVDQUmr:
340 case X86::VMOVAPSmr:
341 case X86::VMOVUPSmr:
342 case X86::VMOVAPDmr:
343 case X86::VMOVUPDmr:
344 case X86::VMOVDQAmr:
345 case X86::VMOVDQUmr:
346 case X86::VMOVUPSZ128mr:
347 case X86::VMOVAPSZ128mr:
348 case X86::VMOVUPSZ128mr_NOVLX:
349 case X86::VMOVAPSZ128mr_NOVLX:
350 case X86::VMOVUPDZ128mr:
351 case X86::VMOVAPDZ128mr:
352 case X86::VMOVDQA32Z128mr:
353 case X86::VMOVDQU32Z128mr:
354 case X86::VMOVDQA64Z128mr:
355 case X86::VMOVDQU64Z128mr:
356 case X86::VMOVDQU8Z128mr:
357 case X86::VMOVDQU16Z128mr:
358 MemBytes = 16;
359 return true;
360 case X86::VMOVUPSYmr:
361 case X86::VMOVAPSYmr:
362 case X86::VMOVUPDYmr:
363 case X86::VMOVAPDYmr:
364 case X86::VMOVDQUYmr:
365 case X86::VMOVDQAYmr:
366 case X86::VMOVUPSZ256mr:
367 case X86::VMOVAPSZ256mr:
368 case X86::VMOVUPSZ256mr_NOVLX:
369 case X86::VMOVAPSZ256mr_NOVLX:
370 case X86::VMOVUPDZ256mr:
371 case X86::VMOVAPDZ256mr:
372 case X86::VMOVDQU8Z256mr:
373 case X86::VMOVDQU16Z256mr:
374 case X86::VMOVDQA32Z256mr:
375 case X86::VMOVDQU32Z256mr:
376 case X86::VMOVDQA64Z256mr:
377 case X86::VMOVDQU64Z256mr:
378 MemBytes = 32;
379 return true;
380 case X86::VMOVUPSZmr:
381 case X86::VMOVAPSZmr:
382 case X86::VMOVUPDZmr:
383 case X86::VMOVAPDZmr:
384 case X86::VMOVDQU8Zmr:
385 case X86::VMOVDQU16Zmr:
386 case X86::VMOVDQA32Zmr:
387 case X86::VMOVDQU32Zmr:
388 case X86::VMOVDQA64Zmr:
389 case X86::VMOVDQU64Zmr:
390 MemBytes = 64;
391 return true;
392 }
393 return false;
394 }
395
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397 int &FrameIndex) const {
398 unsigned Dummy;
399 return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
400 }
401
402 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
403 int &FrameIndex,
404 unsigned &MemBytes) const {
405 if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407 return MI.getOperand(0).getReg();
408 return 0;
409 }
410
411 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
412 int &FrameIndex) const {
413 unsigned Dummy;
414 if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
415 unsigned Reg;
416 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
417 return Reg;
418 // Check for post-frame index elimination operations
419 SmallVector<const MachineMemOperand *, 1> Accesses;
420 if (hasLoadFromStackSlot(MI, Accesses)) {
421 FrameIndex =
422 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
423 ->getFrameIndex();
424 return 1;
425 }
426 }
427 return 0;
428 }
429
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431 int &FrameIndex) const {
432 unsigned Dummy;
433 return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
434 }
435
436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
437 int &FrameIndex,
438 unsigned &MemBytes) const {
439 if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
441 isFrameOperand(MI, 0, FrameIndex))
442 return MI.getOperand(X86::AddrNumOperands).getReg();
443 return 0;
444 }
445
446 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
447 int &FrameIndex) const {
448 unsigned Dummy;
449 if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
450 unsigned Reg;
451 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
452 return Reg;
453 // Check for post-frame index elimination operations
454 SmallVector<const MachineMemOperand *, 1> Accesses;
455 if (hasStoreToStackSlot(MI, Accesses)) {
456 FrameIndex =
457 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
458 ->getFrameIndex();
459 return 1;
460 }
461 }
462 return 0;
463 }
464
465 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
467 // Don't waste compile time scanning use-def chains of physregs.
468 if (!Register::isVirtualRegister(BaseReg))
469 return false;
470 bool isPICBase = false;
471 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
472 E = MRI.def_instr_end(); I != E; ++I) {
473 MachineInstr *DefMI = &*I;
474 if (DefMI->getOpcode() != X86::MOVPC32r)
475 return false;
476 assert(!isPICBase && "More than one PIC base?");
477 isPICBase = true;
478 }
479 return isPICBase;
480 }
481
482 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
483 AliasAnalysis *AA) const {
484 switch (MI.getOpcode()) {
485 default:
486 // This function should only be called for opcodes with the ReMaterializable
487 // flag set.
488 llvm_unreachable("Unknown rematerializable operation!");
489 break;
490
491 case X86::LOAD_STACK_GUARD:
492 case X86::AVX1_SETALLONES:
493 case X86::AVX2_SETALLONES:
494 case X86::AVX512_128_SET0:
495 case X86::AVX512_256_SET0:
496 case X86::AVX512_512_SET0:
497 case X86::AVX512_512_SETALLONES:
498 case X86::AVX512_FsFLD0SD:
499 case X86::AVX512_FsFLD0SS:
500 case X86::AVX512_FsFLD0F128:
501 case X86::AVX_SET0:
502 case X86::FsFLD0SD:
503 case X86::FsFLD0SS:
504 case X86::FsFLD0F128:
505 case X86::KSET0D:
506 case X86::KSET0Q:
507 case X86::KSET0W:
508 case X86::KSET1D:
509 case X86::KSET1Q:
510 case X86::KSET1W:
511 case X86::MMX_SET0:
512 case X86::MOV32ImmSExti8:
513 case X86::MOV32r0:
514 case X86::MOV32r1:
515 case X86::MOV32r_1:
516 case X86::MOV32ri64:
517 case X86::MOV64ImmSExti8:
518 case X86::V_SET0:
519 case X86::V_SETALLONES:
520 case X86::MOV16ri:
521 case X86::MOV32ri:
522 case X86::MOV64ri:
523 case X86::MOV64ri32:
524 case X86::MOV8ri:
525 return true;
526
527 case X86::MOV8rm:
528 case X86::MOV8rm_NOREX:
529 case X86::MOV16rm:
530 case X86::MOV32rm:
531 case X86::MOV64rm:
532 case X86::MOVSSrm:
533 case X86::MOVSSrm_alt:
534 case X86::MOVSDrm:
535 case X86::MOVSDrm_alt:
536 case X86::MOVAPSrm:
537 case X86::MOVUPSrm:
538 case X86::MOVAPDrm:
539 case X86::MOVUPDrm:
540 case X86::MOVDQArm:
541 case X86::MOVDQUrm:
542 case X86::VMOVSSrm:
543 case X86::VMOVSSrm_alt:
544 case X86::VMOVSDrm:
545 case X86::VMOVSDrm_alt:
546 case X86::VMOVAPSrm:
547 case X86::VMOVUPSrm:
548 case X86::VMOVAPDrm:
549 case X86::VMOVUPDrm:
550 case X86::VMOVDQArm:
551 case X86::VMOVDQUrm:
552 case X86::VMOVAPSYrm:
553 case X86::VMOVUPSYrm:
554 case X86::VMOVAPDYrm:
555 case X86::VMOVUPDYrm:
556 case X86::VMOVDQAYrm:
557 case X86::VMOVDQUYrm:
558 case X86::MMX_MOVD64rm:
559 case X86::MMX_MOVQ64rm:
560 // AVX-512
561 case X86::VMOVSSZrm:
562 case X86::VMOVSSZrm_alt:
563 case X86::VMOVSDZrm:
564 case X86::VMOVSDZrm_alt:
565 case X86::VMOVAPDZ128rm:
566 case X86::VMOVAPDZ256rm:
567 case X86::VMOVAPDZrm:
568 case X86::VMOVAPSZ128rm:
569 case X86::VMOVAPSZ256rm:
570 case X86::VMOVAPSZ128rm_NOVLX:
571 case X86::VMOVAPSZ256rm_NOVLX:
572 case X86::VMOVAPSZrm:
573 case X86::VMOVDQA32Z128rm:
574 case X86::VMOVDQA32Z256rm:
575 case X86::VMOVDQA32Zrm:
576 case X86::VMOVDQA64Z128rm:
577 case X86::VMOVDQA64Z256rm:
578 case X86::VMOVDQA64Zrm:
579 case X86::VMOVDQU16Z128rm:
580 case X86::VMOVDQU16Z256rm:
581 case X86::VMOVDQU16Zrm:
582 case X86::VMOVDQU32Z128rm:
583 case X86::VMOVDQU32Z256rm:
584 case X86::VMOVDQU32Zrm:
585 case X86::VMOVDQU64Z128rm:
586 case X86::VMOVDQU64Z256rm:
587 case X86::VMOVDQU64Zrm:
588 case X86::VMOVDQU8Z128rm:
589 case X86::VMOVDQU8Z256rm:
590 case X86::VMOVDQU8Zrm:
591 case X86::VMOVUPDZ128rm:
592 case X86::VMOVUPDZ256rm:
593 case X86::VMOVUPDZrm:
594 case X86::VMOVUPSZ128rm:
595 case X86::VMOVUPSZ256rm:
596 case X86::VMOVUPSZ128rm_NOVLX:
597 case X86::VMOVUPSZ256rm_NOVLX:
598 case X86::VMOVUPSZrm: {
599 // Loads from constant pools are trivially rematerializable.
600 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
601 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
602 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
603 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
604 MI.isDereferenceableInvariantLoad(AA)) {
605 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
606 if (BaseReg == 0 || BaseReg == X86::RIP)
607 return true;
608 // Allow re-materialization of PIC load.
609 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
610 return false;
611 const MachineFunction &MF = *MI.getParent()->getParent();
612 const MachineRegisterInfo &MRI = MF.getRegInfo();
613 return regIsPICBase(BaseReg, MRI);
614 }
615 return false;
616 }
617
618 case X86::LEA32r:
619 case X86::LEA64r: {
620 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
621 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
622 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
623 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
624 // lea fi#, lea GV, etc. are all rematerializable.
625 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
626 return true;
627 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
628 if (BaseReg == 0)
629 return true;
630 // Allow re-materialization of lea PICBase + x.
631 const MachineFunction &MF = *MI.getParent()->getParent();
632 const MachineRegisterInfo &MRI = MF.getRegInfo();
633 return regIsPICBase(BaseReg, MRI);
634 }
635 return false;
636 }
637 }
638 }
639
640 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
641 MachineBasicBlock::iterator I,
642 unsigned DestReg, unsigned SubIdx,
643 const MachineInstr &Orig,
644 const TargetRegisterInfo &TRI) const {
645 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
646 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
647 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
648 // effects.
649 int Value;
650 switch (Orig.getOpcode()) {
651 case X86::MOV32r0: Value = 0; break;
652 case X86::MOV32r1: Value = 1; break;
653 case X86::MOV32r_1: Value = -1; break;
654 default:
655 llvm_unreachable("Unexpected instruction!");
656 }
657
658 const DebugLoc &DL = Orig.getDebugLoc();
659 BuildMI(MBB, I, DL, get(X86::MOV32ri))
660 .add(Orig.getOperand(0))
661 .addImm(Value);
662 } else {
663 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
664 MBB.insert(I, MI);
665 }
666
667 MachineInstr &NewMI = *std::prev(I);
668 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
669 }
670
671 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
672 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
673 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
674 MachineOperand &MO = MI.getOperand(i);
675 if (MO.isReg() && MO.isDef() &&
676 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
677 return true;
678 }
679 }
680 return false;
681 }
682
683 /// Check whether the shift count for a machine operand is non-zero.
684 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
685 unsigned ShiftAmtOperandIdx) {
686 // The shift count is six bits with the REX.W prefix and five bits without.
687 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
688 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
689 return Imm & ShiftCountMask;
690 }
691
692 /// Check whether the given shift count is appropriate
693 /// can be represented by a LEA instruction.
694 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
695 // Left shift instructions can be transformed into load-effective-address
696 // instructions if we can encode them appropriately.
697 // A LEA instruction utilizes a SIB byte to encode its scale factor.
698 // The SIB.scale field is two bits wide which means that we can encode any
699 // shift amount less than 4.
700 return ShAmt < 4 && ShAmt > 0;
701 }
702
703 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
704 unsigned Opc, bool AllowSP, Register &NewSrc,
705 bool &isKill, MachineOperand &ImplicitOp,
706 LiveVariables *LV) const {
707 MachineFunction &MF = *MI.getParent()->getParent();
708 const TargetRegisterClass *RC;
709 if (AllowSP) {
710 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
711 } else {
712 RC = Opc != X86::LEA32r ?
713 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
714 }
715 Register SrcReg = Src.getReg();
716
717 // For both LEA64 and LEA32 the register already has essentially the right
718 // type (32-bit or 64-bit) we may just need to forbid SP.
719 if (Opc != X86::LEA64_32r) {
720 NewSrc = SrcReg;
721 isKill = Src.isKill();
722 assert(!Src.isUndef() && "Undef op doesn't need optimization");
723
724 if (Register::isVirtualRegister(NewSrc) &&
725 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
726 return false;
727
728 return true;
729 }
730
731 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
732 // another we need to add 64-bit registers to the final MI.
733 if (Register::isPhysicalRegister(SrcReg)) {
734 ImplicitOp = Src;
735 ImplicitOp.setImplicit();
736
737 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
738 isKill = Src.isKill();
739 assert(!Src.isUndef() && "Undef op doesn't need optimization");
740 } else {
741 // Virtual register of the wrong class, we have to create a temporary 64-bit
742 // vreg to feed into the LEA.
743 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
744 MachineInstr *Copy =
745 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
746 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
747 .add(Src);
748
749 // Which is obviously going to be dead after we're done with it.
750 isKill = true;
751
752 if (LV)
753 LV->replaceKillInstruction(SrcReg, MI, *Copy);
754 }
755
756 // We've set all the parameters without issue.
757 return true;
758 }
759
760 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
761 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
762 LiveVariables *LV, bool Is8BitOp) const {
763 // We handle 8-bit adds and various 16-bit opcodes in the switch below.
764 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
765 assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
766 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
767 "Unexpected type for LEA transform");
768
769 // TODO: For a 32-bit target, we need to adjust the LEA variables with
770 // something like this:
771 // Opcode = X86::LEA32r;
772 // InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
773 // OutRegLEA =
774 // Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
775 // : RegInfo.createVirtualRegister(&X86::GR32RegClass);
776 if (!Subtarget.is64Bit())
777 return nullptr;
778
779 unsigned Opcode = X86::LEA64_32r;
780 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
781 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
782
783 // Build and insert into an implicit UNDEF value. This is OK because
784 // we will be shifting and then extracting the lower 8/16-bits.
785 // This has the potential to cause partial register stall. e.g.
786 // movw (%rbp,%rcx,2), %dx
787 // leal -65(%rdx), %esi
788 // But testing has shown this *does* help performance in 64-bit mode (at
789 // least on modern x86 machines).
790 MachineBasicBlock::iterator MBBI = MI.getIterator();
791 Register Dest = MI.getOperand(0).getReg();
792 Register Src = MI.getOperand(1).getReg();
793 bool IsDead = MI.getOperand(0).isDead();
794 bool IsKill = MI.getOperand(1).isKill();
795 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
796 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
797 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
798 MachineInstr *InsMI =
799 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
800 .addReg(InRegLEA, RegState::Define, SubReg)
801 .addReg(Src, getKillRegState(IsKill));
802
803 MachineInstrBuilder MIB =
804 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
805 switch (MIOpc) {
806 default: llvm_unreachable("Unreachable!");
807 case X86::SHL8ri:
808 case X86::SHL16ri: {
809 unsigned ShAmt = MI.getOperand(2).getImm();
810 MIB.addReg(0).addImm(1ULL << ShAmt)
811 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
812 break;
813 }
814 case X86::INC8r:
815 case X86::INC16r:
816 addRegOffset(MIB, InRegLEA, true, 1);
817 break;
818 case X86::DEC8r:
819 case X86::DEC16r:
820 addRegOffset(MIB, InRegLEA, true, -1);
821 break;
822 case X86::ADD8ri:
823 case X86::ADD8ri_DB:
824 case X86::ADD16ri:
825 case X86::ADD16ri8:
826 case X86::ADD16ri_DB:
827 case X86::ADD16ri8_DB:
828 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
829 break;
830 case X86::ADD8rr:
831 case X86::ADD8rr_DB:
832 case X86::ADD16rr:
833 case X86::ADD16rr_DB: {
834 Register Src2 = MI.getOperand(2).getReg();
835 bool IsKill2 = MI.getOperand(2).isKill();
836 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
837 unsigned InRegLEA2 = 0;
838 MachineInstr *InsMI2 = nullptr;
839 if (Src == Src2) {
840 // ADD8rr/ADD16rr killed %reg1028, %reg1028
841 // just a single insert_subreg.
842 addRegReg(MIB, InRegLEA, true, InRegLEA, false);
843 } else {
844 if (Subtarget.is64Bit())
845 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
846 else
847 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
848 // Build and insert into an implicit UNDEF value. This is OK because
849 // we will be shifting and then extracting the lower 8/16-bits.
850 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
851 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
852 .addReg(InRegLEA2, RegState::Define, SubReg)
853 .addReg(Src2, getKillRegState(IsKill2));
854 addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
855 }
856 if (LV && IsKill2 && InsMI2)
857 LV->replaceKillInstruction(Src2, MI, *InsMI2);
858 break;
859 }
860 }
861
862 MachineInstr *NewMI = MIB;
863 MachineInstr *ExtMI =
864 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
865 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
866 .addReg(OutRegLEA, RegState::Kill, SubReg);
867
868 if (LV) {
869 // Update live variables.
870 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
871 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
872 if (IsKill)
873 LV->replaceKillInstruction(Src, MI, *InsMI);
874 if (IsDead)
875 LV->replaceKillInstruction(Dest, MI, *ExtMI);
876 }
877
878 return ExtMI;
879 }
880
881 /// This method must be implemented by targets that
882 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
883 /// may be able to convert a two-address instruction into a true
884 /// three-address instruction on demand. This allows the X86 target (for
885 /// example) to convert ADD and SHL instructions into LEA instructions if they
886 /// would require register copies due to two-addressness.
887 ///
888 /// This method returns a null pointer if the transformation cannot be
889 /// performed, otherwise it returns the new instruction.
890 ///
891 MachineInstr *
892 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
893 MachineInstr &MI, LiveVariables *LV) const {
894 // The following opcodes also sets the condition code register(s). Only
895 // convert them to equivalent lea if the condition code register def's
896 // are dead!
897 if (hasLiveCondCodeDef(MI))
898 return nullptr;
899
900 MachineFunction &MF = *MI.getParent()->getParent();
901 // All instructions input are two-addr instructions. Get the known operands.
902 const MachineOperand &Dest = MI.getOperand(0);
903 const MachineOperand &Src = MI.getOperand(1);
904
905 // Ideally, operations with undef should be folded before we get here, but we
906 // can't guarantee it. Bail out because optimizing undefs is a waste of time.
907 // Without this, we have to forward undef state to new register operands to
908 // avoid machine verifier errors.
909 if (Src.isUndef())
910 return nullptr;
911 if (MI.getNumOperands() > 2)
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
913 return nullptr;
914
915 MachineInstr *NewMI = nullptr;
916 bool Is64Bit = Subtarget.is64Bit();
917
918 bool Is8BitOp = false;
919 unsigned MIOpc = MI.getOpcode();
920 switch (MIOpc) {
921 default: llvm_unreachable("Unreachable!");
922 case X86::SHL64ri: {
923 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
924 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
925 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
926
927 // LEA can't handle RSP.
928 if (Register::isVirtualRegister(Src.getReg()) &&
929 !MF.getRegInfo().constrainRegClass(Src.getReg(),
930 &X86::GR64_NOSPRegClass))
931 return nullptr;
932
933 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
934 .add(Dest)
935 .addReg(0)
936 .addImm(1ULL << ShAmt)
937 .add(Src)
938 .addImm(0)
939 .addReg(0);
940 break;
941 }
942 case X86::SHL32ri: {
943 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
944 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
945 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
946
947 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
948
949 // LEA can't handle ESP.
950 bool isKill;
951 Register SrcReg;
952 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
953 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
954 SrcReg, isKill, ImplicitOp, LV))
955 return nullptr;
956
957 MachineInstrBuilder MIB =
958 BuildMI(MF, MI.getDebugLoc(), get(Opc))
959 .add(Dest)
960 .addReg(0)
961 .addImm(1ULL << ShAmt)
962 .addReg(SrcReg, getKillRegState(isKill))
963 .addImm(0)
964 .addReg(0);
965 if (ImplicitOp.getReg() != 0)
966 MIB.add(ImplicitOp);
967 NewMI = MIB;
968
969 break;
970 }
971 case X86::SHL8ri:
972 Is8BitOp = true;
973 LLVM_FALLTHROUGH;
974 case X86::SHL16ri: {
975 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
976 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
977 if (!isTruncatedShiftCountForLEA(ShAmt))
978 return nullptr;
979 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
980 }
981 case X86::INC64r:
982 case X86::INC32r: {
983 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
984 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
985 (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
986 bool isKill;
987 Register SrcReg;
988 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
989 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
990 ImplicitOp, LV))
991 return nullptr;
992
993 MachineInstrBuilder MIB =
994 BuildMI(MF, MI.getDebugLoc(), get(Opc))
995 .add(Dest)
996 .addReg(SrcReg, getKillRegState(isKill));
997 if (ImplicitOp.getReg() != 0)
998 MIB.add(ImplicitOp);
999
1000 NewMI = addOffset(MIB, 1);
1001 break;
1002 }
1003 case X86::DEC64r:
1004 case X86::DEC32r: {
1005 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1006 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1007 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1008
1009 bool isKill;
1010 Register SrcReg;
1011 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1012 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1013 ImplicitOp, LV))
1014 return nullptr;
1015
1016 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1017 .add(Dest)
1018 .addReg(SrcReg, getKillRegState(isKill));
1019 if (ImplicitOp.getReg() != 0)
1020 MIB.add(ImplicitOp);
1021
1022 NewMI = addOffset(MIB, -1);
1023
1024 break;
1025 }
1026 case X86::DEC8r:
1027 case X86::INC8r:
1028 Is8BitOp = true;
1029 LLVM_FALLTHROUGH;
1030 case X86::DEC16r:
1031 case X86::INC16r:
1032 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1033 case X86::ADD64rr:
1034 case X86::ADD64rr_DB:
1035 case X86::ADD32rr:
1036 case X86::ADD32rr_DB: {
1037 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1038 unsigned Opc;
1039 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1040 Opc = X86::LEA64r;
1041 else
1042 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1043
1044 bool isKill;
1045 Register SrcReg;
1046 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1047 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1048 SrcReg, isKill, ImplicitOp, LV))
1049 return nullptr;
1050
1051 const MachineOperand &Src2 = MI.getOperand(2);
1052 bool isKill2;
1053 Register SrcReg2;
1054 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1055 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1056 SrcReg2, isKill2, ImplicitOp2, LV))
1057 return nullptr;
1058
1059 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1060 if (ImplicitOp.getReg() != 0)
1061 MIB.add(ImplicitOp);
1062 if (ImplicitOp2.getReg() != 0)
1063 MIB.add(ImplicitOp2);
1064
1065 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1066 if (LV && Src2.isKill())
1067 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1068 break;
1069 }
1070 case X86::ADD8rr:
1071 case X86::ADD8rr_DB:
1072 Is8BitOp = true;
1073 LLVM_FALLTHROUGH;
1074 case X86::ADD16rr:
1075 case X86::ADD16rr_DB:
1076 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1077 case X86::ADD64ri32:
1078 case X86::ADD64ri8:
1079 case X86::ADD64ri32_DB:
1080 case X86::ADD64ri8_DB:
1081 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1082 NewMI = addOffset(
1083 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1084 MI.getOperand(2));
1085 break;
1086 case X86::ADD32ri:
1087 case X86::ADD32ri8:
1088 case X86::ADD32ri_DB:
1089 case X86::ADD32ri8_DB: {
1090 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1091 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1092
1093 bool isKill;
1094 Register SrcReg;
1095 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1096 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1097 SrcReg, isKill, ImplicitOp, LV))
1098 return nullptr;
1099
1100 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1101 .add(Dest)
1102 .addReg(SrcReg, getKillRegState(isKill));
1103 if (ImplicitOp.getReg() != 0)
1104 MIB.add(ImplicitOp);
1105
1106 NewMI = addOffset(MIB, MI.getOperand(2));
1107 break;
1108 }
1109 case X86::ADD8ri:
1110 case X86::ADD8ri_DB:
1111 Is8BitOp = true;
1112 LLVM_FALLTHROUGH;
1113 case X86::ADD16ri:
1114 case X86::ADD16ri8:
1115 case X86::ADD16ri_DB:
1116 case X86::ADD16ri8_DB:
1117 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1118 case X86::SUB8ri:
1119 case X86::SUB16ri8:
1120 case X86::SUB16ri:
1121 /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1122 return nullptr;
1123 case X86::SUB32ri8:
1124 case X86::SUB32ri: {
1125 int64_t Imm = MI.getOperand(2).getImm();
1126 if (!isInt<32>(-Imm))
1127 return nullptr;
1128
1129 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1130 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1131
1132 bool isKill;
1133 Register SrcReg;
1134 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1135 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1136 SrcReg, isKill, ImplicitOp, LV))
1137 return nullptr;
1138
1139 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1140 .add(Dest)
1141 .addReg(SrcReg, getKillRegState(isKill));
1142 if (ImplicitOp.getReg() != 0)
1143 MIB.add(ImplicitOp);
1144
1145 NewMI = addOffset(MIB, -Imm);
1146 break;
1147 }
1148
1149 case X86::SUB64ri8:
1150 case X86::SUB64ri32: {
1151 int64_t Imm = MI.getOperand(2).getImm();
1152 if (!isInt<32>(-Imm))
1153 return nullptr;
1154
1155 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1156
1157 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1158 get(X86::LEA64r)).add(Dest).add(Src);
1159 NewMI = addOffset(MIB, -Imm);
1160 break;
1161 }
1162
1163 case X86::VMOVDQU8Z128rmk:
1164 case X86::VMOVDQU8Z256rmk:
1165 case X86::VMOVDQU8Zrmk:
1166 case X86::VMOVDQU16Z128rmk:
1167 case X86::VMOVDQU16Z256rmk:
1168 case X86::VMOVDQU16Zrmk:
1169 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1170 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1171 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk:
1172 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1173 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1174 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk:
1175 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk:
1176 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk:
1177 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
1178 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
1179 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
1180 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk:
1181 case X86::VBROADCASTSDZ256mk:
1182 case X86::VBROADCASTSDZmk:
1183 case X86::VBROADCASTSSZ128mk:
1184 case X86::VBROADCASTSSZ256mk:
1185 case X86::VBROADCASTSSZmk:
1186 case X86::VPBROADCASTDZ128mk:
1187 case X86::VPBROADCASTDZ256mk:
1188 case X86::VPBROADCASTDZmk:
1189 case X86::VPBROADCASTQZ128mk:
1190 case X86::VPBROADCASTQZ256mk:
1191 case X86::VPBROADCASTQZmk: {
1192 unsigned Opc;
1193 switch (MIOpc) {
1194 default: llvm_unreachable("Unreachable!");
1195 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
1196 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
1197 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
1198 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1199 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1200 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
1201 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1202 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1203 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1204 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1205 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1206 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1207 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1208 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1209 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1210 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1211 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1212 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1213 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1214 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1215 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
1216 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1217 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1218 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
1219 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
1220 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
1221 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
1222 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
1223 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
1224 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
1225 case X86::VBROADCASTSDZ256mk: Opc = X86::VBLENDMPDZ256rmbk; break;
1226 case X86::VBROADCASTSDZmk: Opc = X86::VBLENDMPDZrmbk; break;
1227 case X86::VBROADCASTSSZ128mk: Opc = X86::VBLENDMPSZ128rmbk; break;
1228 case X86::VBROADCASTSSZ256mk: Opc = X86::VBLENDMPSZ256rmbk; break;
1229 case X86::VBROADCASTSSZmk: Opc = X86::VBLENDMPSZrmbk; break;
1230 case X86::VPBROADCASTDZ128mk: Opc = X86::VPBLENDMDZ128rmbk; break;
1231 case X86::VPBROADCASTDZ256mk: Opc = X86::VPBLENDMDZ256rmbk; break;
1232 case X86::VPBROADCASTDZmk: Opc = X86::VPBLENDMDZrmbk; break;
1233 case X86::VPBROADCASTQZ128mk: Opc = X86::VPBLENDMQZ128rmbk; break;
1234 case X86::VPBROADCASTQZ256mk: Opc = X86::VPBLENDMQZ256rmbk; break;
1235 case X86::VPBROADCASTQZmk: Opc = X86::VPBLENDMQZrmbk; break;
1236 }
1237
1238 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1239 .add(Dest)
1240 .add(MI.getOperand(2))
1241 .add(Src)
1242 .add(MI.getOperand(3))
1243 .add(MI.getOperand(4))
1244 .add(MI.getOperand(5))
1245 .add(MI.getOperand(6))
1246 .add(MI.getOperand(7));
1247 break;
1248 }
1249
1250 case X86::VMOVDQU8Z128rrk:
1251 case X86::VMOVDQU8Z256rrk:
1252 case X86::VMOVDQU8Zrrk:
1253 case X86::VMOVDQU16Z128rrk:
1254 case X86::VMOVDQU16Z256rrk:
1255 case X86::VMOVDQU16Zrrk:
1256 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1257 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1258 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk:
1259 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1260 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1261 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk:
1262 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk:
1263 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk:
1264 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk:
1265 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk:
1266 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk:
1267 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: {
1268 unsigned Opc;
1269 switch (MIOpc) {
1270 default: llvm_unreachable("Unreachable!");
1271 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break;
1272 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break;
1273 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break;
1274 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1275 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1276 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break;
1277 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1278 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1279 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1280 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1281 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1282 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1283 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1284 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1285 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1286 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1287 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1288 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1289 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1290 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1291 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break;
1292 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1293 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1294 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break;
1295 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break;
1296 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break;
1297 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break;
1298 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break;
1299 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break;
1300 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break;
1301 }
1302
1303 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1304 .add(Dest)
1305 .add(MI.getOperand(2))
1306 .add(Src)
1307 .add(MI.getOperand(3));
1308 break;
1309 }
1310 }
1311
1312 if (!NewMI) return nullptr;
1313
1314 if (LV) { // Update live variables
1315 if (Src.isKill())
1316 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1317 if (Dest.isDead())
1318 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1319 }
1320
1321 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1322 return NewMI;
1323 }
1324
1325 /// This determines which of three possible cases of a three source commute
1326 /// the source indexes correspond to taking into account any mask operands.
1327 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1328 /// possible.
1329 /// Case 0 - Possible to commute the first and second operands.
1330 /// Case 1 - Possible to commute the first and third operands.
1331 /// Case 2 - Possible to commute the second and third operands.
1332 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1333 unsigned SrcOpIdx2) {
1334 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1335 if (SrcOpIdx1 > SrcOpIdx2)
1336 std::swap(SrcOpIdx1, SrcOpIdx2);
1337
1338 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1339 if (X86II::isKMasked(TSFlags)) {
1340 Op2++;
1341 Op3++;
1342 }
1343
1344 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1345 return 0;
1346 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1347 return 1;
1348 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1349 return 2;
1350 llvm_unreachable("Unknown three src commute case.");
1351 }
1352
1353 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1354 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1355 const X86InstrFMA3Group &FMA3Group) const {
1356
1357 unsigned Opc = MI.getOpcode();
1358
1359 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1360 // analysis. The commute optimization is legal only if all users of FMA*_Int
1361 // use only the lowest element of the FMA*_Int instruction. Such analysis are
1362 // not implemented yet. So, just return 0 in that case.
1363 // When such analysis are available this place will be the right place for
1364 // calling it.
1365 assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1366 "Intrinsic instructions can't commute operand 1");
1367
1368 // Determine which case this commute is or if it can't be done.
1369 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1370 SrcOpIdx2);
1371 assert(Case < 3 && "Unexpected case number!");
1372
1373 // Define the FMA forms mapping array that helps to map input FMA form
1374 // to output FMA form to preserve the operation semantics after
1375 // commuting the operands.
1376 const unsigned Form132Index = 0;
1377 const unsigned Form213Index = 1;
1378 const unsigned Form231Index = 2;
1379 static const unsigned FormMapping[][3] = {
1380 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1381 // FMA132 A, C, b; ==> FMA231 C, A, b;
1382 // FMA213 B, A, c; ==> FMA213 A, B, c;
1383 // FMA231 C, A, b; ==> FMA132 A, C, b;
1384 { Form231Index, Form213Index, Form132Index },
1385 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1386 // FMA132 A, c, B; ==> FMA132 B, c, A;
1387 // FMA213 B, a, C; ==> FMA231 C, a, B;
1388 // FMA231 C, a, B; ==> FMA213 B, a, C;
1389 { Form132Index, Form231Index, Form213Index },
1390 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1391 // FMA132 a, C, B; ==> FMA213 a, B, C;
1392 // FMA213 b, A, C; ==> FMA132 b, C, A;
1393 // FMA231 c, A, B; ==> FMA231 c, B, A;
1394 { Form213Index, Form132Index, Form231Index }
1395 };
1396
1397 unsigned FMAForms[3];
1398 FMAForms[0] = FMA3Group.get132Opcode();
1399 FMAForms[1] = FMA3Group.get213Opcode();
1400 FMAForms[2] = FMA3Group.get231Opcode();
1401 unsigned FormIndex;
1402 for (FormIndex = 0; FormIndex < 3; FormIndex++)
1403 if (Opc == FMAForms[FormIndex])
1404 break;
1405
1406 // Everything is ready, just adjust the FMA opcode and return it.
1407 FormIndex = FormMapping[Case][FormIndex];
1408 return FMAForms[FormIndex];
1409 }
1410
1411 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1412 unsigned SrcOpIdx2) {
1413 // Determine which case this commute is or if it can't be done.
1414 unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1415 SrcOpIdx2);
1416 assert(Case < 3 && "Unexpected case value!");
1417
1418 // For each case we need to swap two pairs of bits in the final immediate.
1419 static const uint8_t SwapMasks[3][4] = {
1420 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1421 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1422 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1423 };
1424
1425 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1426 // Clear out the bits we are swapping.
1427 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1428 SwapMasks[Case][2] | SwapMasks[Case][3]);
1429 // If the immediate had a bit of the pair set, then set the opposite bit.
1430 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1431 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1432 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1433 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1434 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1435 }
1436
1437 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1438 // commuted.
1439 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1440 #define VPERM_CASES(Suffix) \
1441 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
1442 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
1443 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
1444 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
1445 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
1446 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
1447 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
1448 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
1449 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
1450 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
1451 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
1452 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
1453
1454 #define VPERM_CASES_BROADCAST(Suffix) \
1455 VPERM_CASES(Suffix) \
1456 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
1457 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
1458 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
1459 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1460 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1461 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
1462
1463 switch (Opcode) {
1464 default: return false;
1465 VPERM_CASES(B)
1466 VPERM_CASES_BROADCAST(D)
1467 VPERM_CASES_BROADCAST(PD)
1468 VPERM_CASES_BROADCAST(PS)
1469 VPERM_CASES_BROADCAST(Q)
1470 VPERM_CASES(W)
1471 return true;
1472 }
1473 #undef VPERM_CASES_BROADCAST
1474 #undef VPERM_CASES
1475 }
1476
1477 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1478 // from the I opcode to the T opcode and vice versa.
1479 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1480 #define VPERM_CASES(Orig, New) \
1481 case X86::Orig##128rr: return X86::New##128rr; \
1482 case X86::Orig##128rrkz: return X86::New##128rrkz; \
1483 case X86::Orig##128rm: return X86::New##128rm; \
1484 case X86::Orig##128rmkz: return X86::New##128rmkz; \
1485 case X86::Orig##256rr: return X86::New##256rr; \
1486 case X86::Orig##256rrkz: return X86::New##256rrkz; \
1487 case X86::Orig##256rm: return X86::New##256rm; \
1488 case X86::Orig##256rmkz: return X86::New##256rmkz; \
1489 case X86::Orig##rr: return X86::New##rr; \
1490 case X86::Orig##rrkz: return X86::New##rrkz; \
1491 case X86::Orig##rm: return X86::New##rm; \
1492 case X86::Orig##rmkz: return X86::New##rmkz;
1493
1494 #define VPERM_CASES_BROADCAST(Orig, New) \
1495 VPERM_CASES(Orig, New) \
1496 case X86::Orig##128rmb: return X86::New##128rmb; \
1497 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1498 case X86::Orig##256rmb: return X86::New##256rmb; \
1499 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1500 case X86::Orig##rmb: return X86::New##rmb; \
1501 case X86::Orig##rmbkz: return X86::New##rmbkz;
1502
1503 switch (Opcode) {
1504 VPERM_CASES(VPERMI2B, VPERMT2B)
1505 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D)
1506 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1507 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1508 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q)
1509 VPERM_CASES(VPERMI2W, VPERMT2W)
1510 VPERM_CASES(VPERMT2B, VPERMI2B)
1511 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D)
1512 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1513 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1514 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q)
1515 VPERM_CASES(VPERMT2W, VPERMI2W)
1516 }
1517
1518 llvm_unreachable("Unreachable!");
1519 #undef VPERM_CASES_BROADCAST
1520 #undef VPERM_CASES
1521 }
1522
1523 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1524 unsigned OpIdx1,
1525 unsigned OpIdx2) const {
1526 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1527 if (NewMI)
1528 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1529 return MI;
1530 };
1531
1532 switch (MI.getOpcode()) {
1533 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1534 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1535 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1536 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1537 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1538 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1539 unsigned Opc;
1540 unsigned Size;
1541 switch (MI.getOpcode()) {
1542 default: llvm_unreachable("Unreachable!");
1543 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1544 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1545 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1546 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1547 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1548 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1549 }
1550 unsigned Amt = MI.getOperand(3).getImm();
1551 auto &WorkingMI = cloneIfNew(MI);
1552 WorkingMI.setDesc(get(Opc));
1553 WorkingMI.getOperand(3).setImm(Size - Amt);
1554 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1555 OpIdx1, OpIdx2);
1556 }
1557 case X86::PFSUBrr:
1558 case X86::PFSUBRrr: {
1559 // PFSUB x, y: x = x - y
1560 // PFSUBR x, y: x = y - x
1561 unsigned Opc =
1562 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1563 auto &WorkingMI = cloneIfNew(MI);
1564 WorkingMI.setDesc(get(Opc));
1565 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1566 OpIdx1, OpIdx2);
1567 }
1568 case X86::BLENDPDrri:
1569 case X86::BLENDPSrri:
1570 case X86::VBLENDPDrri:
1571 case X86::VBLENDPSrri:
1572 // If we're optimizing for size, try to use MOVSD/MOVSS.
1573 if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1574 unsigned Mask, Opc;
1575 switch (MI.getOpcode()) {
1576 default: llvm_unreachable("Unreachable!");
1577 case X86::BLENDPDrri: Opc = X86::MOVSDrr; Mask = 0x03; break;
1578 case X86::BLENDPSrri: Opc = X86::MOVSSrr; Mask = 0x0F; break;
1579 case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1580 case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1581 }
1582 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1583 auto &WorkingMI = cloneIfNew(MI);
1584 WorkingMI.setDesc(get(Opc));
1585 WorkingMI.RemoveOperand(3);
1586 return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1587 /*NewMI=*/false,
1588 OpIdx1, OpIdx2);
1589 }
1590 }
1591 LLVM_FALLTHROUGH;
1592 case X86::PBLENDWrri:
1593 case X86::VBLENDPDYrri:
1594 case X86::VBLENDPSYrri:
1595 case X86::VPBLENDDrri:
1596 case X86::VPBLENDWrri:
1597 case X86::VPBLENDDYrri:
1598 case X86::VPBLENDWYrri:{
1599 int8_t Mask;
1600 switch (MI.getOpcode()) {
1601 default: llvm_unreachable("Unreachable!");
1602 case X86::BLENDPDrri: Mask = (int8_t)0x03; break;
1603 case X86::BLENDPSrri: Mask = (int8_t)0x0F; break;
1604 case X86::PBLENDWrri: Mask = (int8_t)0xFF; break;
1605 case X86::VBLENDPDrri: Mask = (int8_t)0x03; break;
1606 case X86::VBLENDPSrri: Mask = (int8_t)0x0F; break;
1607 case X86::VBLENDPDYrri: Mask = (int8_t)0x0F; break;
1608 case X86::VBLENDPSYrri: Mask = (int8_t)0xFF; break;
1609 case X86::VPBLENDDrri: Mask = (int8_t)0x0F; break;
1610 case X86::VPBLENDWrri: Mask = (int8_t)0xFF; break;
1611 case X86::VPBLENDDYrri: Mask = (int8_t)0xFF; break;
1612 case X86::VPBLENDWYrri: Mask = (int8_t)0xFF; break;
1613 }
1614 // Only the least significant bits of Imm are used.
1615 // Using int8_t to ensure it will be sign extended to the int64_t that
1616 // setImm takes in order to match isel behavior.
1617 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1618 auto &WorkingMI = cloneIfNew(MI);
1619 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1620 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1621 OpIdx1, OpIdx2);
1622 }
1623 case X86::INSERTPSrr:
1624 case X86::VINSERTPSrr:
1625 case X86::VINSERTPSZrr: {
1626 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1627 unsigned ZMask = Imm & 15;
1628 unsigned DstIdx = (Imm >> 4) & 3;
1629 unsigned SrcIdx = (Imm >> 6) & 3;
1630
1631 // We can commute insertps if we zero 2 of the elements, the insertion is
1632 // "inline" and we don't override the insertion with a zero.
1633 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1634 countPopulation(ZMask) == 2) {
1635 unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1636 assert(AltIdx < 4 && "Illegal insertion index");
1637 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1638 auto &WorkingMI = cloneIfNew(MI);
1639 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1640 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1641 OpIdx1, OpIdx2);
1642 }
1643 return nullptr;
1644 }
1645 case X86::MOVSDrr:
1646 case X86::MOVSSrr:
1647 case X86::VMOVSDrr:
1648 case X86::VMOVSSrr:{
1649 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1650 if (Subtarget.hasSSE41()) {
1651 unsigned Mask, Opc;
1652 switch (MI.getOpcode()) {
1653 default: llvm_unreachable("Unreachable!");
1654 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break;
1655 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break;
1656 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1657 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1658 }
1659
1660 auto &WorkingMI = cloneIfNew(MI);
1661 WorkingMI.setDesc(get(Opc));
1662 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1663 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1664 OpIdx1, OpIdx2);
1665 }
1666
1667 // Convert to SHUFPD.
1668 assert(MI.getOpcode() == X86::MOVSDrr &&
1669 "Can only commute MOVSDrr without SSE4.1");
1670
1671 auto &WorkingMI = cloneIfNew(MI);
1672 WorkingMI.setDesc(get(X86::SHUFPDrri));
1673 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
1674 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1675 OpIdx1, OpIdx2);
1676 }
1677 case X86::SHUFPDrri: {
1678 // Commute to MOVSD.
1679 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1680 auto &WorkingMI = cloneIfNew(MI);
1681 WorkingMI.setDesc(get(X86::MOVSDrr));
1682 WorkingMI.RemoveOperand(3);
1683 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1684 OpIdx1, OpIdx2);
1685 }
1686 case X86::PCLMULQDQrr:
1687 case X86::VPCLMULQDQrr:
1688 case X86::VPCLMULQDQYrr:
1689 case X86::VPCLMULQDQZrr:
1690 case X86::VPCLMULQDQZ128rr:
1691 case X86::VPCLMULQDQZ256rr: {
1692 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1693 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1694 unsigned Imm = MI.getOperand(3).getImm();
1695 unsigned Src1Hi = Imm & 0x01;
1696 unsigned Src2Hi = Imm & 0x10;
1697 auto &WorkingMI = cloneIfNew(MI);
1698 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1699 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1700 OpIdx1, OpIdx2);
1701 }
1702 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
1703 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
1704 case X86::VPCMPBZrri: case X86::VPCMPUBZrri:
1705 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
1706 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
1707 case X86::VPCMPDZrri: case X86::VPCMPUDZrri:
1708 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
1709 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
1710 case X86::VPCMPQZrri: case X86::VPCMPUQZrri:
1711 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
1712 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
1713 case X86::VPCMPWZrri: case X86::VPCMPUWZrri:
1714 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1715 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1716 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik:
1717 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1718 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1719 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik:
1720 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1721 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1722 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik:
1723 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1724 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1725 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: {
1726 // Flip comparison mode immediate (if necessary).
1727 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1728 Imm = X86::getSwappedVPCMPImm(Imm);
1729 auto &WorkingMI = cloneIfNew(MI);
1730 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1731 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1732 OpIdx1, OpIdx2);
1733 }
1734 case X86::VPCOMBri: case X86::VPCOMUBri:
1735 case X86::VPCOMDri: case X86::VPCOMUDri:
1736 case X86::VPCOMQri: case X86::VPCOMUQri:
1737 case X86::VPCOMWri: case X86::VPCOMUWri: {
1738 // Flip comparison mode immediate (if necessary).
1739 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1740 Imm = X86::getSwappedVPCOMImm(Imm);
1741 auto &WorkingMI = cloneIfNew(MI);
1742 WorkingMI.getOperand(3).setImm(Imm);
1743 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1744 OpIdx1, OpIdx2);
1745 }
1746 case X86::VCMPSDZrr:
1747 case X86::VCMPSSZrr:
1748 case X86::VCMPPDZrri:
1749 case X86::VCMPPSZrri:
1750 case X86::VCMPPDZ128rri:
1751 case X86::VCMPPSZ128rri:
1752 case X86::VCMPPDZ256rri:
1753 case X86::VCMPPSZ256rri:
1754 case X86::VCMPPDZrrik:
1755 case X86::VCMPPSZrrik:
1756 case X86::VCMPPDZ128rrik:
1757 case X86::VCMPPSZ128rrik:
1758 case X86::VCMPPDZ256rrik:
1759 case X86::VCMPPSZ256rrik: {
1760 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x1f;
1761 Imm = X86::getSwappedVCMPImm(Imm);
1762 auto &WorkingMI = cloneIfNew(MI);
1763 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1764 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1765 OpIdx1, OpIdx2);
1766 }
1767 case X86::VPERM2F128rr:
1768 case X86::VPERM2I128rr: {
1769 // Flip permute source immediate.
1770 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1771 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1772 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1773 auto &WorkingMI = cloneIfNew(MI);
1774 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1775 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1776 OpIdx1, OpIdx2);
1777 }
1778 case X86::MOVHLPSrr:
1779 case X86::UNPCKHPDrr:
1780 case X86::VMOVHLPSrr:
1781 case X86::VUNPCKHPDrr:
1782 case X86::VMOVHLPSZrr:
1783 case X86::VUNPCKHPDZ128rr: {
1784 assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1785
1786 unsigned Opc = MI.getOpcode();
1787 switch (Opc) {
1788 default: llvm_unreachable("Unreachable!");
1789 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
1790 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
1791 case X86::VMOVHLPSrr: Opc = X86::VUNPCKHPDrr; break;
1792 case X86::VUNPCKHPDrr: Opc = X86::VMOVHLPSrr; break;
1793 case X86::VMOVHLPSZrr: Opc = X86::VUNPCKHPDZ128rr; break;
1794 case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr; break;
1795 }
1796 auto &WorkingMI = cloneIfNew(MI);
1797 WorkingMI.setDesc(get(Opc));
1798 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1799 OpIdx1, OpIdx2);
1800 }
1801 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
1802 auto &WorkingMI = cloneIfNew(MI);
1803 unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1804 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1805 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1806 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1807 OpIdx1, OpIdx2);
1808 }
1809 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
1810 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
1811 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
1812 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
1813 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
1814 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
1815 case X86::VPTERNLOGDZrrik:
1816 case X86::VPTERNLOGDZ128rrik:
1817 case X86::VPTERNLOGDZ256rrik:
1818 case X86::VPTERNLOGQZrrik:
1819 case X86::VPTERNLOGQZ128rrik:
1820 case X86::VPTERNLOGQZ256rrik:
1821 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
1822 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1823 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1824 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
1825 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1826 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1827 case X86::VPTERNLOGDZ128rmbi:
1828 case X86::VPTERNLOGDZ256rmbi:
1829 case X86::VPTERNLOGDZrmbi:
1830 case X86::VPTERNLOGQZ128rmbi:
1831 case X86::VPTERNLOGQZ256rmbi:
1832 case X86::VPTERNLOGQZrmbi:
1833 case X86::VPTERNLOGDZ128rmbikz:
1834 case X86::VPTERNLOGDZ256rmbikz:
1835 case X86::VPTERNLOGDZrmbikz:
1836 case X86::VPTERNLOGQZ128rmbikz:
1837 case X86::VPTERNLOGQZ256rmbikz:
1838 case X86::VPTERNLOGQZrmbikz: {
1839 auto &WorkingMI = cloneIfNew(MI);
1840 commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1841 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1842 OpIdx1, OpIdx2);
1843 }
1844 default: {
1845 if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1846 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1847 auto &WorkingMI = cloneIfNew(MI);
1848 WorkingMI.setDesc(get(Opc));
1849 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1850 OpIdx1, OpIdx2);
1851 }
1852
1853 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1854 MI.getDesc().TSFlags);
1855 if (FMA3Group) {
1856 unsigned Opc =
1857 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1858 auto &WorkingMI = cloneIfNew(MI);
1859 WorkingMI.setDesc(get(Opc));
1860 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1861 OpIdx1, OpIdx2);
1862 }
1863
1864 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1865 }
1866 }
1867 }
1868
1869 bool
1870 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1871 unsigned &SrcOpIdx1,
1872 unsigned &SrcOpIdx2,
1873 bool IsIntrinsic) const {
1874 uint64_t TSFlags = MI.getDesc().TSFlags;
1875
1876 unsigned FirstCommutableVecOp = 1;
1877 unsigned LastCommutableVecOp = 3;
1878 unsigned KMaskOp = -1U;
1879 if (X86II::isKMasked(TSFlags)) {
1880 // For k-zero-masked operations it is Ok to commute the first vector
1881 // operand.
1882 // For regular k-masked operations a conservative choice is done as the
1883 // elements of the first vector operand, for which the corresponding bit
1884 // in the k-mask operand is set to 0, are copied to the result of the
1885 // instruction.
1886 // TODO/FIXME: The commute still may be legal if it is known that the
1887 // k-mask operand is set to either all ones or all zeroes.
1888 // It is also Ok to commute the 1st operand if all users of MI use only
1889 // the elements enabled by the k-mask operand. For example,
1890 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1891 // : v1[i];
1892 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1893 // // Ok, to commute v1 in FMADD213PSZrk.
1894
1895 // The k-mask operand has index = 2 for masked and zero-masked operations.
1896 KMaskOp = 2;
1897
1898 // The operand with index = 1 is used as a source for those elements for
1899 // which the corresponding bit in the k-mask is set to 0.
1900 if (X86II::isKMergeMasked(TSFlags))
1901 FirstCommutableVecOp = 3;
1902
1903 LastCommutableVecOp++;
1904 } else if (IsIntrinsic) {
1905 // Commuting the first operand of an intrinsic instruction isn't possible
1906 // unless we can prove that only the lowest element of the result is used.
1907 FirstCommutableVecOp = 2;
1908 }
1909
1910 if (isMem(MI, LastCommutableVecOp))
1911 LastCommutableVecOp--;
1912
1913 // Only the first RegOpsNum operands are commutable.
1914 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1915 // that the operand is not specified/fixed.
1916 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1917 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1918 SrcOpIdx1 == KMaskOp))
1919 return false;
1920 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1921 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1922 SrcOpIdx2 == KMaskOp))
1923 return false;
1924
1925 // Look for two different register operands assumed to be commutable
1926 // regardless of the FMA opcode. The FMA opcode is adjusted later.
1927 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1928 SrcOpIdx2 == CommuteAnyOperandIndex) {
1929 unsigned CommutableOpIdx2 = SrcOpIdx2;
1930
1931 // At least one of operands to be commuted is not specified and
1932 // this method is free to choose appropriate commutable operands.
1933 if (SrcOpIdx1 == SrcOpIdx2)
1934 // Both of operands are not fixed. By default set one of commutable
1935 // operands to the last register operand of the instruction.
1936 CommutableOpIdx2 = LastCommutableVecOp;
1937 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1938 // Only one of operands is not fixed.
1939 CommutableOpIdx2 = SrcOpIdx1;
1940
1941 // CommutableOpIdx2 is well defined now. Let's choose another commutable
1942 // operand and assign its index to CommutableOpIdx1.
1943 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1944
1945 unsigned CommutableOpIdx1;
1946 for (CommutableOpIdx1 = LastCommutableVecOp;
1947 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1948 // Just ignore and skip the k-mask operand.
1949 if (CommutableOpIdx1 == KMaskOp)
1950 continue;
1951
1952 // The commuted operands must have different registers.
1953 // Otherwise, the commute transformation does not change anything and
1954 // is useless then.
1955 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1956 break;
1957 }
1958
1959 // No appropriate commutable operands were found.
1960 if (CommutableOpIdx1 < FirstCommutableVecOp)
1961 return false;
1962
1963 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1964 // to return those values.
1965 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1966 CommutableOpIdx1, CommutableOpIdx2))
1967 return false;
1968 }
1969
1970 return true;
1971 }
1972
1973 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1974 unsigned &SrcOpIdx1,
1975 unsigned &SrcOpIdx2) const {
1976 const MCInstrDesc &Desc = MI.getDesc();
1977 if (!Desc.isCommutable())
1978 return false;
1979
1980 switch (MI.getOpcode()) {
1981 case X86::CMPSDrr:
1982 case X86::CMPSSrr:
1983 case X86::CMPPDrri:
1984 case X86::CMPPSrri:
1985 case X86::VCMPSDrr:
1986 case X86::VCMPSSrr:
1987 case X86::VCMPPDrri:
1988 case X86::VCMPPSrri:
1989 case X86::VCMPPDYrri:
1990 case X86::VCMPPSYrri:
1991 case X86::VCMPSDZrr:
1992 case X86::VCMPSSZrr:
1993 case X86::VCMPPDZrri:
1994 case X86::VCMPPSZrri:
1995 case X86::VCMPPDZ128rri:
1996 case X86::VCMPPSZ128rri:
1997 case X86::VCMPPDZ256rri:
1998 case X86::VCMPPSZ256rri:
1999 case X86::VCMPPDZrrik:
2000 case X86::VCMPPSZrrik:
2001 case X86::VCMPPDZ128rrik:
2002 case X86::VCMPPSZ128rrik:
2003 case X86::VCMPPDZ256rrik:
2004 case X86::VCMPPSZ256rrik: {
2005 unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2006
2007 // Float comparison can be safely commuted for
2008 // Ordered/Unordered/Equal/NotEqual tests
2009 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2010 switch (Imm) {
2011 default:
2012 // EVEX versions can be commuted.
2013 if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2014 break;
2015 return false;
2016 case 0x00: // EQUAL
2017 case 0x03: // UNORDERED
2018 case 0x04: // NOT EQUAL
2019 case 0x07: // ORDERED
2020 break;
2021 }
2022
2023 // The indices of the commutable operands are 1 and 2 (or 2 and 3
2024 // when masked).
2025 // Assign them to the returned operand indices here.
2026 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2027 2 + OpOffset);
2028 }
2029 case X86::MOVSSrr:
2030 // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2031 // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2032 // AVX implies sse4.1.
2033 if (Subtarget.hasSSE41())
2034 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2035 return false;
2036 case X86::SHUFPDrri:
2037 // We can commute this to MOVSD.
2038 if (MI.getOperand(3).getImm() == 0x02)
2039 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2040 return false;
2041 case X86::MOVHLPSrr:
2042 case X86::UNPCKHPDrr:
2043 case X86::VMOVHLPSrr:
2044 case X86::VUNPCKHPDrr:
2045 case X86::VMOVHLPSZrr:
2046 case X86::VUNPCKHPDZ128rr:
2047 if (Subtarget.hasSSE2())
2048 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2049 return false;
2050 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi:
2051 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi:
2052 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi:
2053 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi:
2054 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi:
2055 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi:
2056 case X86::VPTERNLOGDZrrik:
2057 case X86::VPTERNLOGDZ128rrik:
2058 case X86::VPTERNLOGDZ256rrik:
2059 case X86::VPTERNLOGQZrrik:
2060 case X86::VPTERNLOGQZ128rrik:
2061 case X86::VPTERNLOGQZ256rrik:
2062 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz:
2063 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2064 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2065 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz:
2066 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2067 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2068 case X86::VPTERNLOGDZ128rmbi:
2069 case X86::VPTERNLOGDZ256rmbi:
2070 case X86::VPTERNLOGDZrmbi:
2071 case X86::VPTERNLOGQZ128rmbi:
2072 case X86::VPTERNLOGQZ256rmbi:
2073 case X86::VPTERNLOGQZrmbi:
2074 case X86::VPTERNLOGDZ128rmbikz:
2075 case X86::VPTERNLOGDZ256rmbikz:
2076 case X86::VPTERNLOGDZrmbikz:
2077 case X86::VPTERNLOGQZ128rmbikz:
2078 case X86::VPTERNLOGQZ256rmbikz:
2079 case X86::VPTERNLOGQZrmbikz:
2080 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2081 case X86::VPDPWSSDZ128r:
2082 case X86::VPDPWSSDZ128rk:
2083 case X86::VPDPWSSDZ128rkz:
2084 case X86::VPDPWSSDZ256r:
2085 case X86::VPDPWSSDZ256rk:
2086 case X86::VPDPWSSDZ256rkz:
2087 case X86::VPDPWSSDZr:
2088 case X86::VPDPWSSDZrk:
2089 case X86::VPDPWSSDZrkz:
2090 case X86::VPDPWSSDSZ128r:
2091 case X86::VPDPWSSDSZ128rk:
2092 case X86::VPDPWSSDSZ128rkz:
2093 case X86::VPDPWSSDSZ256r:
2094 case X86::VPDPWSSDSZ256rk:
2095 case X86::VPDPWSSDSZ256rkz:
2096 case X86::VPDPWSSDSZr:
2097 case X86::VPDPWSSDSZrk:
2098 case X86::VPDPWSSDSZrkz:
2099 case X86::VPMADD52HUQZ128r:
2100 case X86::VPMADD52HUQZ128rk:
2101 case X86::VPMADD52HUQZ128rkz:
2102 case X86::VPMADD52HUQZ256r:
2103 case X86::VPMADD52HUQZ256rk:
2104 case X86::VPMADD52HUQZ256rkz:
2105 case X86::VPMADD52HUQZr:
2106 case X86::VPMADD52HUQZrk:
2107 case X86::VPMADD52HUQZrkz:
2108 case X86::VPMADD52LUQZ128r:
2109 case X86::VPMADD52LUQZ128rk:
2110 case X86::VPMADD52LUQZ128rkz:
2111 case X86::VPMADD52LUQZ256r:
2112 case X86::VPMADD52LUQZ256rk:
2113 case X86::VPMADD52LUQZ256rkz:
2114 case X86::VPMADD52LUQZr:
2115 case X86::VPMADD52LUQZrk:
2116 case X86::VPMADD52LUQZrkz: {
2117 unsigned CommutableOpIdx1 = 2;
2118 unsigned CommutableOpIdx2 = 3;
2119 if (X86II::isKMasked(Desc.TSFlags)) {
2120 // Skip the mask register.
2121 ++CommutableOpIdx1;
2122 ++CommutableOpIdx2;
2123 }
2124 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2125 CommutableOpIdx1, CommutableOpIdx2))
2126 return false;
2127 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2128 !MI.getOperand(SrcOpIdx2).isReg())
2129 // No idea.
2130 return false;
2131 return true;
2132 }
2133
2134 default:
2135 const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2136 MI.getDesc().TSFlags);
2137 if (FMA3Group)
2138 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2139 FMA3Group->isIntrinsic());
2140
2141 // Handled masked instructions since we need to skip over the mask input
2142 // and the preserved input.
2143 if (X86II::isKMasked(Desc.TSFlags)) {
2144 // First assume that the first input is the mask operand and skip past it.
2145 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2146 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2147 // Check if the first input is tied. If there isn't one then we only
2148 // need to skip the mask operand which we did above.
2149 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2150 MCOI::TIED_TO) != -1)) {
2151 // If this is zero masking instruction with a tied operand, we need to
2152 // move the first index back to the first input since this must
2153 // be a 3 input instruction and we want the first two non-mask inputs.
2154 // Otherwise this is a 2 input instruction with a preserved input and
2155 // mask, so we need to move the indices to skip one more input.
2156 if (X86II::isKMergeMasked(Desc.TSFlags)) {
2157 ++CommutableOpIdx1;
2158 ++CommutableOpIdx2;
2159 } else {
2160 --CommutableOpIdx1;
2161 }
2162 }
2163
2164 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2165 CommutableOpIdx1, CommutableOpIdx2))
2166 return false;
2167
2168 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2169 !MI.getOperand(SrcOpIdx2).isReg())
2170 // No idea.
2171 return false;
2172 return true;
2173 }
2174
2175 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2176 }
2177 return false;
2178 }
2179
2180 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2181 switch (MI.getOpcode()) {
2182 default: return X86::COND_INVALID;
2183 case X86::JCC_1:
2184 return static_cast<X86::CondCode>(
2185 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2186 }
2187 }
2188
2189 /// Return condition code of a SETCC opcode.
2190 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2191 switch (MI.getOpcode()) {
2192 default: return X86::COND_INVALID;
2193 case X86::SETCCr: case X86::SETCCm:
2194 return static_cast<X86::CondCode>(
2195 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2196 }
2197 }
2198
2199 /// Return condition code of a CMov opcode.
2200 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2201 switch (MI.getOpcode()) {
2202 default: return X86::COND_INVALID;
2203 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2204 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2205 return static_cast<X86::CondCode>(
2206 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2207 }
2208 }
2209
2210 /// Return the inverse of the specified condition,
2211 /// e.g. turning COND_E to COND_NE.
2212 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2213 switch (CC) {
2214 default: llvm_unreachable("Illegal condition code!");
2215 case X86::COND_E: return X86::COND_NE;
2216 case X86::COND_NE: return X86::COND_E;
2217 case X86::COND_L: return X86::COND_GE;
2218 case X86::COND_LE: return X86::COND_G;
2219 case X86::COND_G: return X86::COND_LE;
2220 case X86::COND_GE: return X86::COND_L;
2221 case X86::COND_B: return X86::COND_AE;
2222 case X86::COND_BE: return X86::COND_A;
2223 case X86::COND_A: return X86::COND_BE;
2224 case X86::COND_AE: return X86::COND_B;
2225 case X86::COND_S: return X86::COND_NS;
2226 case X86::COND_NS: return X86::COND_S;
2227 case X86::COND_P: return X86::COND_NP;
2228 case X86::COND_NP: return X86::COND_P;
2229 case X86::COND_O: return X86::COND_NO;
2230 case X86::COND_NO: return X86::COND_O;
2231 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
2232 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2233 }
2234 }
2235
2236 /// Assuming the flags are set by MI(a,b), return the condition code if we
2237 /// modify the instructions such that flags are set by MI(b,a).
2238 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2239 switch (CC) {
2240 default: return X86::COND_INVALID;
2241 case X86::COND_E: return X86::COND_E;
2242 case X86::COND_NE: return X86::COND_NE;
2243 case X86::COND_L: return X86::COND_G;
2244 case X86::COND_LE: return X86::COND_GE;
2245 case X86::COND_G: return X86::COND_L;
2246 case X86::COND_GE: return X86::COND_LE;
2247 case X86::COND_B: return X86::COND_A;
2248 case X86::COND_BE: return X86::COND_AE;
2249 case X86::COND_A: return X86::COND_B;
2250 case X86::COND_AE: return X86::COND_BE;
2251 }
2252 }
2253
2254 std::pair<X86::CondCode, bool>
2255 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2256 X86::CondCode CC = X86::COND_INVALID;
2257 bool NeedSwap = false;
2258 switch (Predicate) {
2259 default: break;
2260 // Floating-point Predicates
2261 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
2262 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
2263 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
2264 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
2265 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
2266 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
2267 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
2268 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
2269 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
2270 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
2271 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
2272 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
2273 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
2274 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2275
2276 // Integer Predicates
2277 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
2278 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
2279 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
2280 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
2281 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
2282 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
2283 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
2284 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
2285 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
2286 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
2287 }
2288
2289 return std::make_pair(CC, NeedSwap);
2290 }
2291
2292 /// Return a setcc opcode based on whether it has memory operand.
2293 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2294 return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2295 }
2296
2297 /// Return a cmov opcode for the given register size in bytes, and operand type.
2298 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2299 switch(RegBytes) {
2300 default: llvm_unreachable("Illegal register size!");
2301 case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2302 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2303 case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2304 }
2305 }
2306
2307 /// Get the VPCMP immediate for the given condition.
2308 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2309 switch (CC) {
2310 default: llvm_unreachable("Unexpected SETCC condition");
2311 case ISD::SETNE: return 4;
2312 case ISD::SETEQ: return 0;
2313 case ISD::SETULT:
2314 case ISD::SETLT: return 1;
2315 case ISD::SETUGT:
2316 case ISD::SETGT: return 6;
2317 case ISD::SETUGE:
2318 case ISD::SETGE: return 5;
2319 case ISD::SETULE:
2320 case ISD::SETLE: return 2;
2321 }
2322 }
2323
2324 /// Get the VPCMP immediate if the operands are swapped.
2325 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2326 switch (Imm) {
2327 default: llvm_unreachable("Unreachable!");
2328 case 0x01: Imm = 0x06; break; // LT -> NLE
2329 case 0x02: Imm = 0x05; break; // LE -> NLT
2330 case 0x05: Imm = 0x02; break; // NLT -> LE
2331 case 0x06: Imm = 0x01; break; // NLE -> LT
2332 case 0x00: // EQ
2333 case 0x03: // FALSE
2334 case 0x04: // NE
2335 case 0x07: // TRUE
2336 break;
2337 }
2338
2339 return Imm;
2340 }
2341
2342 /// Get the VPCOM immediate if the operands are swapped.
2343 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2344 switch (Imm) {
2345 default: llvm_unreachable("Unreachable!");
2346 case 0x00: Imm = 0x02; break; // LT -> GT
2347 case 0x01: Imm = 0x03; break; // LE -> GE
2348 case 0x02: Imm = 0x00; break; // GT -> LT
2349 case 0x03: Imm = 0x01; break; // GE -> LE
2350 case 0x04: // EQ
2351 case 0x05: // NE
2352 case 0x06: // FALSE
2353 case 0x07: // TRUE
2354 break;
2355 }
2356
2357 return Imm;
2358 }
2359
2360 /// Get the VCMP immediate if the operands are swapped.
2361 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2362 // Only need the lower 2 bits to distinquish.
2363 switch (Imm & 0x3) {
2364 default: llvm_unreachable("Unreachable!");
2365 case 0x00: case 0x03:
2366 // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2367 break;
2368 case 0x01: case 0x02:
2369 // Need to toggle bits 3:0. Bit 4 stays the same.
2370 Imm ^= 0xf;
2371 break;
2372 }
2373
2374 return Imm;
2375 }
2376
2377 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2378 if (!MI.isTerminator()) return false;
2379
2380 // Conditional branch is a special case.
2381 if (MI.isBranch() && !MI.isBarrier())
2382 return true;
2383 if (!MI.isPredicable())
2384 return true;
2385 return !isPredicated(MI);
2386 }
2387
2388 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2389 switch (MI.getOpcode()) {
2390 case X86::TCRETURNdi:
2391 case X86::TCRETURNri:
2392 case X86::TCRETURNmi:
2393 case X86::TCRETURNdi64:
2394 case X86::TCRETURNri64:
2395 case X86::TCRETURNmi64:
2396 return true;
2397 default:
2398 return false;
2399 }
2400 }
2401
2402 bool X86InstrInfo::canMakeTailCallConditional(
2403 SmallVectorImpl<MachineOperand> &BranchCond,
2404 const MachineInstr &TailCall) const {
2405 if (TailCall.getOpcode() != X86::TCRETURNdi &&
2406 TailCall.getOpcode() != X86::TCRETURNdi64) {
2407 // Only direct calls can be done with a conditional branch.
2408 return false;
2409 }
2410
2411 const MachineFunction *MF = TailCall.getParent()->getParent();
2412 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2413 // Conditional tail calls confuse the Win64 unwinder.
2414 return false;
2415 }
2416
2417 assert(BranchCond.size() == 1);
2418 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2419 // Can't make a conditional tail call with this condition.
2420 return false;
2421 }
2422
2423 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2424 if (X86FI->getTCReturnAddrDelta() != 0 ||
2425 TailCall.getOperand(1).getImm() != 0) {
2426 // A conditional tail call cannot do any stack adjustment.
2427 return false;
2428 }
2429
2430 return true;
2431 }
2432
2433 void X86InstrInfo::replaceBranchWithTailCall(
2434 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2435 const MachineInstr &TailCall) const {
2436 assert(canMakeTailCallConditional(BranchCond, TailCall));
2437
2438 MachineBasicBlock::iterator I = MBB.end();
2439 while (I != MBB.begin()) {
2440 --I;
2441 if (I->isDebugInstr())
2442 continue;
2443 if (!I->isBranch())
2444 assert(0 && "Can't find the branch to replace!");
2445
2446 X86::CondCode CC = X86::getCondFromBranch(*I);
2447 assert(BranchCond.size() == 1);
2448 if (CC != BranchCond[0].getImm())
2449 continue;
2450
2451 break;
2452 }
2453
2454 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2455 : X86::TCRETURNdi64cc;
2456
2457 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2458 MIB->addOperand(TailCall.getOperand(0)); // Destination.
2459 MIB.addImm(0); // Stack offset (not used).
2460 MIB->addOperand(BranchCond[0]); // Condition.
2461 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2462
2463 // Add implicit uses and defs of all live regs potentially clobbered by the
2464 // call. This way they still appear live across the call.
2465 LivePhysRegs LiveRegs(getRegisterInfo());
2466 LiveRegs.addLiveOuts(MBB);
2467 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2468 LiveRegs.stepForward(*MIB, Clobbers);
2469 for (const auto &C : Clobbers) {
2470 MIB.addReg(C.first, RegState::Implicit);
2471 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2472 }
2473
2474 I->eraseFromParent();
2475 }
2476
2477 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2478 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2479 // fallthrough MBB cannot be identified.
2480 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2481 MachineBasicBlock *TBB) {
2482 // Look for non-EHPad successors other than TBB. If we find exactly one, it
2483 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2484 // and fallthrough MBB. If we find more than one, we cannot identify the
2485 // fallthrough MBB and should return nullptr.
2486 MachineBasicBlock *FallthroughBB = nullptr;
2487 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2488 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2489 continue;
2490 // Return a nullptr if we found more than one fallthrough successor.
2491 if (FallthroughBB && FallthroughBB != TBB)
2492 return nullptr;
2493 FallthroughBB = *SI;
2494 }
2495 return FallthroughBB;
2496 }
2497
2498 bool X86InstrInfo::AnalyzeBranchImpl(
2499 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2500 SmallVectorImpl<MachineOperand> &Cond,
2501 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2502
2503 // Start from the bottom of the block and work up, examining the
2504 // terminator instructions.
2505 MachineBasicBlock::iterator I = MBB.end();
2506 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2507 while (I != MBB.begin()) {
2508 --I;
2509 if (I->isDebugInstr())
2510 continue;
2511
2512 // Working from the bottom, when we see a non-terminator instruction, we're
2513 // done.
2514 if (!isUnpredicatedTerminator(*I))
2515 break;
2516
2517 // A terminator that isn't a branch can't easily be handled by this
2518 // analysis.
2519 if (!I->isBranch())
2520 return true;
2521
2522 // Handle unconditional branches.
2523 if (I->getOpcode() == X86::JMP_1) {
2524 UnCondBrIter = I;
2525
2526 if (!AllowModify) {
2527 TBB = I->getOperand(0).getMBB();
2528 continue;
2529 }
2530
2531 // If the block has any instructions after a JMP, delete them.
2532 while (std::next(I) != MBB.end())
2533 std::next(I)->eraseFromParent();
2534
2535 Cond.clear();
2536 FBB = nullptr;
2537
2538 // Delete the JMP if it's equivalent to a fall-through.
2539 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2540 TBB = nullptr;
2541 I->eraseFromParent();
2542 I = MBB.end();
2543 UnCondBrIter = MBB.end();
2544 continue;
2545 }
2546
2547 // TBB is used to indicate the unconditional destination.
2548 TBB = I->getOperand(0).getMBB();
2549 continue;
2550 }
2551
2552 // Handle conditional branches.
2553 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2554 if (BranchCode == X86::COND_INVALID)
2555 return true; // Can't handle indirect branch.
2556
2557 // In practice we should never have an undef eflags operand, if we do
2558 // abort here as we are not prepared to preserve the flag.
2559 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2560 return true;
2561
2562 // Working from the bottom, handle the first conditional branch.
2563 if (Cond.empty()) {
2564 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2565 if (AllowModify && UnCondBrIter != MBB.end() &&
2566 MBB.isLayoutSuccessor(TargetBB)) {
2567 // If we can modify the code and it ends in something like:
2568 //
2569 // jCC L1
2570 // jmp L2
2571 // L1:
2572 // ...
2573 // L2:
2574 //
2575 // Then we can change this to:
2576 //
2577 // jnCC L2
2578 // L1:
2579 // ...
2580 // L2:
2581 //
2582 // Which is a bit more efficient.
2583 // We conditionally jump to the fall-through block.
2584 BranchCode = GetOppositeBranchCondition(BranchCode);
2585 MachineBasicBlock::iterator OldInst = I;
2586
2587 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2588 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2589 .addImm(BranchCode);
2590 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2591 .addMBB(TargetBB);
2592
2593 OldInst->eraseFromParent();
2594 UnCondBrIter->eraseFromParent();
2595
2596 // Restart the analysis.
2597 UnCondBrIter = MBB.end();
2598 I = MBB.end();
2599 continue;
2600 }
2601
2602 FBB = TBB;
2603 TBB = I->getOperand(0).getMBB();
2604 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2605 CondBranches.push_back(&*I);
2606 continue;
2607 }
2608
2609 // Handle subsequent conditional branches. Only handle the case where all
2610 // conditional branches branch to the same destination and their condition
2611 // opcodes fit one of the special multi-branch idioms.
2612 assert(Cond.size() == 1);
2613 assert(TBB);
2614
2615 // If the conditions are the same, we can leave them alone.
2616 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2617 auto NewTBB = I->getOperand(0).getMBB();
2618 if (OldBranchCode == BranchCode && TBB == NewTBB)
2619 continue;
2620
2621 // If they differ, see if they fit one of the known patterns. Theoretically,
2622 // we could handle more patterns here, but we shouldn't expect to see them
2623 // if instruction selection has done a reasonable job.
2624 if (TBB == NewTBB &&
2625 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2626 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2627 BranchCode = X86::COND_NE_OR_P;
2628 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2629 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2630 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2631 return true;
2632
2633 // X86::COND_E_AND_NP usually has two different branch destinations.
2634 //
2635 // JP B1
2636 // JE B2
2637 // JMP B1
2638 // B1:
2639 // B2:
2640 //
2641 // Here this condition branches to B2 only if NP && E. It has another
2642 // equivalent form:
2643 //
2644 // JNE B1
2645 // JNP B2
2646 // JMP B1
2647 // B1:
2648 // B2:
2649 //
2650 // Similarly it branches to B2 only if E && NP. That is why this condition
2651 // is named with COND_E_AND_NP.
2652 BranchCode = X86::COND_E_AND_NP;
2653 } else
2654 return true;
2655
2656 // Update the MachineOperand.
2657 Cond[0].setImm(BranchCode);
2658 CondBranches.push_back(&*I);
2659 }
2660
2661 return false;
2662 }
2663
2664 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2665 MachineBasicBlock *&TBB,
2666 MachineBasicBlock *&FBB,
2667 SmallVectorImpl<MachineOperand> &Cond,
2668 bool AllowModify) const {
2669 SmallVector<MachineInstr *, 4> CondBranches;
2670 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2671 }
2672
2673 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2674 MachineBranchPredicate &MBP,
2675 bool AllowModify) const {
2676 using namespace std::placeholders;
2677
2678 SmallVector<MachineOperand, 4> Cond;
2679 SmallVector<MachineInstr *, 4> CondBranches;
2680 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2681 AllowModify))
2682 return true;
2683
2684 if (Cond.size() != 1)
2685 return true;
2686
2687 assert(MBP.TrueDest && "expected!");
2688
2689 if (!MBP.FalseDest)
2690 MBP.FalseDest = MBB.getNextNode();
2691
2692 const TargetRegisterInfo *TRI = &getRegisterInfo();
2693
2694 MachineInstr *ConditionDef = nullptr;
2695 bool SingleUseCondition = true;
2696
2697 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2698 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2699 ConditionDef = &*I;
2700 break;
2701 }
2702
2703 if (I->readsRegister(X86::EFLAGS, TRI))
2704 SingleUseCondition = false;
2705 }
2706
2707 if (!ConditionDef)
2708 return true;
2709
2710 if (SingleUseCondition) {
2711 for (auto *Succ : MBB.successors())
2712 if (Succ->isLiveIn(X86::EFLAGS))
2713 SingleUseCondition = false;
2714 }
2715
2716 MBP.ConditionDef = ConditionDef;
2717 MBP.SingleUseCondition = SingleUseCondition;
2718
2719 // Currently we only recognize the simple pattern:
2720 //
2721 // test %reg, %reg
2722 // je %label
2723 //
2724 const unsigned TestOpcode =
2725 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2726
2727 if (ConditionDef->getOpcode() == TestOpcode &&
2728 ConditionDef->getNumOperands() == 3 &&
2729 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2730 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2731 MBP.LHS = ConditionDef->getOperand(0);
2732 MBP.RHS = MachineOperand::CreateImm(0);
2733 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2734 ? MachineBranchPredicate::PRED_NE
2735 : MachineBranchPredicate::PRED_EQ;
2736 return false;
2737 }
2738
2739 return true;
2740 }
2741
2742 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2743 int *BytesRemoved) const {
2744 assert(!BytesRemoved && "code size not handled");
2745
2746 MachineBasicBlock::iterator I = MBB.end();
2747 unsigned Count = 0;
2748
2749 while (I != MBB.begin()) {
2750 --I;
2751 if (I->isDebugInstr())
2752 continue;
2753 if (I->getOpcode() != X86::JMP_1 &&
2754 X86::getCondFromBranch(*I) == X86::COND_INVALID)
2755 break;
2756 // Remove the branch.
2757 I->eraseFromParent();
2758 I = MBB.end();
2759 ++Count;
2760 }
2761
2762 return Count;
2763 }
2764
2765 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2766 MachineBasicBlock *TBB,
2767 MachineBasicBlock *FBB,
2768 ArrayRef<MachineOperand> Cond,
2769 const DebugLoc &DL,
2770 int *BytesAdded) const {
2771 // Shouldn't be a fall through.
2772 assert(TBB && "insertBranch must not be told to insert a fallthrough");
2773 assert((Cond.size() == 1 || Cond.size() == 0) &&
2774 "X86 branch conditions have one component!");
2775 assert(!BytesAdded && "code size not handled");
2776
2777 if (Cond.empty()) {
2778 // Unconditional branch?
2779 assert(!FBB && "Unconditional branch with multiple successors!");
2780 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2781 return 1;
2782 }
2783
2784 // If FBB is null, it is implied to be a fall-through block.
2785 bool FallThru = FBB == nullptr;
2786
2787 // Conditional branch.
2788 unsigned Count = 0;
2789 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2790 switch (CC) {
2791 case X86::COND_NE_OR_P:
2792 // Synthesize NE_OR_P with two branches.
2793 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2794 ++Count;
2795 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2796 ++Count;
2797 break;
2798 case X86::COND_E_AND_NP:
2799 // Use the next block of MBB as FBB if it is null.
2800 if (FBB == nullptr) {
2801 FBB = getFallThroughMBB(&MBB, TBB);
2802 assert(FBB && "MBB cannot be the last block in function when the false "
2803 "body is a fall-through.");
2804 }
2805 // Synthesize COND_E_AND_NP with two branches.
2806 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2807 ++Count;
2808 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2809 ++Count;
2810 break;
2811 default: {
2812 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2813 ++Count;
2814 }
2815 }
2816 if (!FallThru) {
2817 // Two-way Conditional branch. Insert the second branch.
2818 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2819 ++Count;
2820 }
2821 return Count;
2822 }
2823
2824 bool X86InstrInfo::
2825 canInsertSelect(const MachineBasicBlock &MBB,
2826 ArrayRef<MachineOperand> Cond,
2827 unsigned TrueReg, unsigned FalseReg,
2828 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2829 // Not all subtargets have cmov instructions.
2830 if (!Subtarget.hasCMov())
2831 return false;
2832 if (Cond.size() != 1)
2833 return false;
2834 // We cannot do the composite conditions, at least not in SSA form.
2835 if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2836 return false;
2837
2838 // Check register classes.
2839 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2840 const TargetRegisterClass *RC =
2841 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2842 if (!RC)
2843 return false;
2844
2845 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2846 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2847 X86::GR32RegClass.hasSubClassEq(RC) ||
2848 X86::GR64RegClass.hasSubClassEq(RC)) {
2849 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2850 // Bridge. Probably Ivy Bridge as well.
2851 CondCycles = 2;
2852 TrueCycles = 2;
2853 FalseCycles = 2;
2854 return true;
2855 }
2856
2857 // Can't do vectors.
2858 return false;
2859 }
2860
2861 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2862 MachineBasicBlock::iterator I,
2863 const DebugLoc &DL, unsigned DstReg,
2864 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2865 unsigned FalseReg) const {
2866 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2867 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2868 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2869 assert(Cond.size() == 1 && "Invalid Cond array");
2870 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2871 false /*HasMemoryOperand*/);
2872 BuildMI(MBB, I, DL, get(Opc), DstReg)
2873 .addReg(FalseReg)
2874 .addReg(TrueReg)
2875 .addImm(Cond[0].getImm());
2876 }
2877
2878 /// Test if the given register is a physical h register.
2879 static bool isHReg(unsigned Reg) {
2880 return X86::GR8_ABCD_HRegClass.contains(Reg);
2881 }
2882
2883 // Try and copy between VR128/VR64 and GR64 registers.
2884 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2885 const X86Subtarget &Subtarget) {
2886 bool HasAVX = Subtarget.hasAVX();
2887 bool HasAVX512 = Subtarget.hasAVX512();
2888
2889 // SrcReg(MaskReg) -> DestReg(GR64)
2890 // SrcReg(MaskReg) -> DestReg(GR32)
2891
2892 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2893 if (X86::VK16RegClass.contains(SrcReg)) {
2894 if (X86::GR64RegClass.contains(DestReg)) {
2895 assert(Subtarget.hasBWI());
2896 return X86::KMOVQrk;
2897 }
2898 if (X86::GR32RegClass.contains(DestReg))
2899 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2900 }
2901
2902 // SrcReg(GR64) -> DestReg(MaskReg)
2903 // SrcReg(GR32) -> DestReg(MaskReg)
2904
2905 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2906 if (X86::VK16RegClass.contains(DestReg)) {
2907 if (X86::GR64RegClass.contains(SrcReg)) {
2908 assert(Subtarget.hasBWI());
2909 return X86::KMOVQkr;
2910 }
2911 if (X86::GR32RegClass.contains(SrcReg))
2912 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2913 }
2914
2915
2916 // SrcReg(VR128) -> DestReg(GR64)
2917 // SrcReg(VR64) -> DestReg(GR64)
2918 // SrcReg(GR64) -> DestReg(VR128)
2919 // SrcReg(GR64) -> DestReg(VR64)
2920
2921 if (X86::GR64RegClass.contains(DestReg)) {
2922 if (X86::VR128XRegClass.contains(SrcReg))
2923 // Copy from a VR128 register to a GR64 register.
2924 return HasAVX512 ? X86::VMOVPQIto64Zrr :
2925 HasAVX ? X86::VMOVPQIto64rr :
2926 X86::MOVPQIto64rr;
2927 if (X86::VR64RegClass.contains(SrcReg))
2928 // Copy from a VR64 register to a GR64 register.
2929 return X86::MMX_MOVD64from64rr;
2930 } else if (X86::GR64RegClass.contains(SrcReg)) {
2931 // Copy from a GR64 register to a VR128 register.
2932 if (X86::VR128XRegClass.contains(DestReg))
2933 return HasAVX512 ? X86::VMOV64toPQIZrr :
2934 HasAVX ? X86::VMOV64toPQIrr :
2935 X86::MOV64toPQIrr;
2936 // Copy from a GR64 register to a VR64 register.
2937 if (X86::VR64RegClass.contains(DestReg))
2938 return X86::MMX_MOVD64to64rr;
2939 }
2940
2941 // SrcReg(VR128) -> DestReg(GR32)
2942 // SrcReg(GR32) -> DestReg(VR128)
2943
2944 if (X86::GR32RegClass.contains(DestReg) &&
2945 X86::VR128XRegClass.contains(SrcReg))
2946 // Copy from a VR128 register to a GR32 register.
2947 return HasAVX512 ? X86::VMOVPDI2DIZrr :
2948 HasAVX ? X86::VMOVPDI2DIrr :
2949 X86::MOVPDI2DIrr;
2950
2951 if (X86::VR128XRegClass.contains(DestReg) &&
2952 X86::GR32RegClass.contains(SrcReg))
2953 // Copy from a VR128 register to a VR128 register.
2954 return HasAVX512 ? X86::VMOVDI2PDIZrr :
2955 HasAVX ? X86::VMOVDI2PDIrr :
2956 X86::MOVDI2PDIrr;
2957 return 0;
2958 }
2959
2960 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2961 MachineBasicBlock::iterator MI,
2962 const DebugLoc &DL, unsigned DestReg,
2963 unsigned SrcReg, bool KillSrc) const {
2964 // First deal with the normal symmetric copies.
2965 bool HasAVX = Subtarget.hasAVX();
2966 bool HasVLX = Subtarget.hasVLX();
2967 unsigned Opc = 0;
2968 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2969 Opc = X86::MOV64rr;
2970 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2971 Opc = X86::MOV32rr;
2972 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2973 Opc = X86::MOV16rr;
2974 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2975 // Copying to or from a physical H register on x86-64 requires a NOREX
2976 // move. Otherwise use a normal move.
2977 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2978 Subtarget.is64Bit()) {
2979 Opc = X86::MOV8rr_NOREX;
2980 // Both operands must be encodable without an REX prefix.
2981 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2982 "8-bit H register can not be copied outside GR8_NOREX");
2983 } else
2984 Opc = X86::MOV8rr;
2985 }
2986 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2987 Opc = X86::MMX_MOVQ64rr;
2988 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2989 if (HasVLX)
2990 Opc = X86::VMOVAPSZ128rr;
2991 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2992 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2993 else {
2994 // If this an extended register and we don't have VLX we need to use a
2995 // 512-bit move.
2996 Opc = X86::VMOVAPSZrr;
2997 const TargetRegisterInfo *TRI = &getRegisterInfo();
2998 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
2999 &X86::VR512RegClass);
3000 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3001 &X86::VR512RegClass);
3002 }
3003 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3004 if (HasVLX)
3005 Opc = X86::VMOVAPSZ256rr;
3006 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3007 Opc = X86::VMOVAPSYrr;
3008 else {
3009 // If this an extended register and we don't have VLX we need to use a
3010 // 512-bit move.
3011 Opc = X86::VMOVAPSZrr;
3012 const TargetRegisterInfo *TRI = &getRegisterInfo();
3013 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3014 &X86::VR512RegClass);
3015 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3016 &X86::VR512RegClass);
3017 }
3018 } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3019 Opc = X86::VMOVAPSZrr;
3020 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3021 else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3022 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3023 if (!Opc)
3024 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3025
3026 if (Opc) {
3027 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3028 .addReg(SrcReg, getKillRegState(KillSrc));
3029 return;
3030 }
3031
3032 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3033 // FIXME: We use a fatal error here because historically LLVM has tried
3034 // lower some of these physreg copies and we want to ensure we get
3035 // reasonable bug reports if someone encounters a case no other testing
3036 // found. This path should be removed after the LLVM 7 release.
3037 report_fatal_error("Unable to copy EFLAGS physical register!");
3038 }
3039
3040 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3041 << RI.getName(DestReg) << '\n');
3042 report_fatal_error("Cannot emit physreg copy instruction");
3043 }
3044
3045 bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
3046 const MachineOperand *&Src,
3047 const MachineOperand *&Dest) const {
3048 if (MI.isMoveReg()) {
3049 Dest = &MI.getOperand(0);
3050 Src = &MI.getOperand(1);
3051 return true;
3052 }
3053 return false;
3054 }
3055
3056 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3057 const TargetRegisterClass *RC,
3058 bool isStackAligned,
3059 const X86Subtarget &STI,
3060 bool load) {
3061 bool HasAVX = STI.hasAVX();
3062 bool HasAVX512 = STI.hasAVX512();
3063 bool HasVLX = STI.hasVLX();
3064
3065 switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3066 default:
3067 llvm_unreachable("Unknown spill size");
3068 case 1:
3069 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3070 if (STI.is64Bit())
3071 // Copying to or from a physical H register on x86-64 requires a NOREX
3072 // move. Otherwise use a normal move.
3073 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3074 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3075 return load ? X86::MOV8rm : X86::MOV8mr;
3076 case 2:
3077 if (X86::VK16RegClass.hasSubClassEq(RC))
3078 return load ? X86::KMOVWkm : X86::KMOVWmk;
3079 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3080 return load ? X86::MOV16rm : X86::MOV16mr;
3081 case 4:
3082 if (X86::GR32RegClass.hasSubClassEq(RC))
3083 return load ? X86::MOV32rm : X86::MOV32mr;
3084 if (X86::FR32XRegClass.hasSubClassEq(RC))
3085 return load ?
3086 (HasAVX512 ? X86::VMOVSSZrm_alt :
3087 HasAVX ? X86::VMOVSSrm_alt :
3088 X86::MOVSSrm_alt) :
3089 (HasAVX512 ? X86::VMOVSSZmr :
3090 HasAVX ? X86::VMOVSSmr :
3091 X86::MOVSSmr);
3092 if (X86::RFP32RegClass.hasSubClassEq(RC))
3093 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3094 if (X86::VK32RegClass.hasSubClassEq(RC)) {
3095 assert(STI.hasBWI() && "KMOVD requires BWI");
3096 return load ? X86::KMOVDkm : X86::KMOVDmk;
3097 }
3098 // All of these mask pair classes have the same spill size, the same kind
3099 // of kmov instructions can be used with all of them.
3100 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3101 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3102 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3103 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3104 X86::VK16PAIRRegClass.hasSubClassEq(RC))
3105 return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3106 llvm_unreachable("Unknown 4-byte regclass");
3107 case 8:
3108 if (X86::GR64RegClass.hasSubClassEq(RC))
3109 return load ? X86::MOV64rm : X86::MOV64mr;
3110 if (X86::FR64XRegClass.hasSubClassEq(RC))
3111 return load ?
3112 (HasAVX512 ? X86::VMOVSDZrm_alt :
3113 HasAVX ? X86::VMOVSDrm_alt :
3114 X86::MOVSDrm_alt) :
3115 (HasAVX512 ? X86::VMOVSDZmr :
3116 HasAVX ? X86::VMOVSDmr :
3117 X86::MOVSDmr);
3118 if (X86::VR64RegClass.hasSubClassEq(RC))
3119 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3120 if (X86::RFP64RegClass.hasSubClassEq(RC))
3121 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3122 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3123 assert(STI.hasBWI() && "KMOVQ requires BWI");
3124 return load ? X86::KMOVQkm : X86::KMOVQmk;
3125 }
3126 llvm_unreachable("Unknown 8-byte regclass");
3127 case 10:
3128 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3129 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3130 case 16: {
3131 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3132 // If stack is realigned we can use aligned stores.
3133 if (isStackAligned)
3134 return load ?
3135 (HasVLX ? X86::VMOVAPSZ128rm :
3136 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3137 HasAVX ? X86::VMOVAPSrm :
3138 X86::MOVAPSrm):
3139 (HasVLX ? X86::VMOVAPSZ128mr :
3140 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3141 HasAVX ? X86::VMOVAPSmr :
3142 X86::MOVAPSmr);
3143 else
3144 return load ?
3145 (HasVLX ? X86::VMOVUPSZ128rm :
3146 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3147 HasAVX ? X86::VMOVUPSrm :
3148 X86::MOVUPSrm):
3149 (HasVLX ? X86::VMOVUPSZ128mr :
3150 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3151 HasAVX ? X86::VMOVUPSmr :
3152 X86::MOVUPSmr);
3153 }
3154 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3155 if (STI.is64Bit())
3156 return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3157 else
3158 return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3159 }
3160 llvm_unreachable("Unknown 16-byte regclass");
3161 }
3162 case 32:
3163 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3164 // If stack is realigned we can use aligned stores.
3165 if (isStackAligned)
3166 return load ?
3167 (HasVLX ? X86::VMOVAPSZ256rm :
3168 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3169 X86::VMOVAPSYrm) :
3170 (HasVLX ? X86::VMOVAPSZ256mr :
3171 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3172 X86::VMOVAPSYmr);
3173 else
3174 return load ?
3175 (HasVLX ? X86::VMOVUPSZ256rm :
3176 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3177 X86::VMOVUPSYrm) :
3178 (HasVLX ? X86::VMOVUPSZ256mr :
3179 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3180 X86::VMOVUPSYmr);
3181 case 64:
3182 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3183 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3184 if (isStackAligned)
3185 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3186 else
3187 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3188 }
3189 }
3190
3191 bool X86InstrInfo::getMemOperandWithOffset(
3192 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3193 const TargetRegisterInfo *TRI) const {
3194 const MCInstrDesc &Desc = MemOp.getDesc();
3195 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3196 if (MemRefBegin < 0)
3197 return false;
3198
3199 MemRefBegin += X86II::getOperandBias(Desc);
3200
3201 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3202 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3203 return false;
3204
3205 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3206 return false;
3207
3208 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3209 X86::NoRegister)
3210 return false;
3211
3212 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3213
3214 // Displacement can be symbolic
3215 if (!DispMO.isImm())
3216 return false;
3217
3218 Offset = DispMO.getImm();
3219
3220 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3221 "operands of type register.");
3222 return true;
3223 }
3224
3225 static unsigned getStoreRegOpcode(unsigned SrcReg,
3226 const TargetRegisterClass *RC,
3227 bool isStackAligned,
3228 const X86Subtarget &STI) {
3229 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3230 }
3231
3232
3233 static unsigned getLoadRegOpcode(unsigned DestReg,
3234 const TargetRegisterClass *RC,
3235 bool isStackAligned,
3236 const X86Subtarget &STI) {
3237 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3238 }
3239
3240 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3241 MachineBasicBlock::iterator MI,
3242 unsigned SrcReg, bool isKill, int FrameIdx,
3243 const TargetRegisterClass *RC,
3244 const TargetRegisterInfo *TRI) const {
3245 const MachineFunction &MF = *MBB.getParent();
3246 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3247 "Stack slot too small for store");
3248 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3249 bool isAligned =
3250 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3251 RI.canRealignStack(MF);
3252 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3253 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3254 .addReg(SrcReg, getKillRegState(isKill));
3255 }
3256
3257 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3258 MachineBasicBlock::iterator MI,
3259 unsigned DestReg, int FrameIdx,
3260 const TargetRegisterClass *RC,
3261 const TargetRegisterInfo *TRI) const {
3262 const MachineFunction &MF = *MBB.getParent();
3263 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3264 bool isAligned =
3265 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3266 RI.canRealignStack(MF);
3267 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3268 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3269 }
3270
3271 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3272 unsigned &SrcReg2, int &CmpMask,
3273 int &CmpValue) const {
3274 switch (MI.getOpcode()) {
3275 default: break;
3276 case X86::CMP64ri32:
3277 case X86::CMP64ri8:
3278 case X86::CMP32ri:
3279 case X86::CMP32ri8:
3280 case X86::CMP16ri:
3281 case X86::CMP16ri8:
3282 case X86::CMP8ri:
3283 SrcReg = MI.getOperand(0).getReg();
3284 SrcReg2 = 0;
3285 if (MI.getOperand(1).isImm()) {
3286 CmpMask = ~0;
3287 CmpValue = MI.getOperand(1).getImm();
3288 } else {
3289 CmpMask = CmpValue = 0;
3290 }
3291 return true;
3292 // A SUB can be used to perform comparison.
3293 case X86::SUB64rm:
3294 case X86::SUB32rm:
3295 case X86::SUB16rm:
3296 case X86::SUB8rm:
3297 SrcReg = MI.getOperand(1).getReg();
3298 SrcReg2 = 0;
3299 CmpMask = 0;
3300 CmpValue = 0;
3301 return true;
3302 case X86::SUB64rr:
3303 case X86::SUB32rr:
3304 case X86::SUB16rr:
3305 case X86::SUB8rr:
3306 SrcReg = MI.getOperand(1).getReg();
3307 SrcReg2 = MI.getOperand(2).getReg();
3308 CmpMask = 0;
3309 CmpValue = 0;
3310 return true;
3311 case X86::SUB64ri32:
3312 case X86::SUB64ri8:
3313 case X86::SUB32ri:
3314 case X86::SUB32ri8:
3315 case X86::SUB16ri:
3316 case X86::SUB16ri8:
3317 case X86::SUB8ri:
3318 SrcReg = MI.getOperand(1).getReg();
3319 SrcReg2 = 0;
3320 if (MI.getOperand(2).isImm()) {
3321 CmpMask = ~0;
3322 CmpValue = MI.getOperand(2).getImm();
3323 } else {
3324 CmpMask = CmpValue = 0;
3325 }
3326 return true;
3327 case X86::CMP64rr:
3328 case X86::CMP32rr:
3329 case X86::CMP16rr:
3330 case X86::CMP8rr:
3331 SrcReg = MI.getOperand(0).getReg();
3332 SrcReg2 = MI.getOperand(1).getReg();
3333 CmpMask = 0;
3334 CmpValue = 0;
3335 return true;
3336 case X86::TEST8rr:
3337 case X86::TEST16rr:
3338 case X86::TEST32rr:
3339 case X86::TEST64rr:
3340 SrcReg = MI.getOperand(0).getReg();
3341 if (MI.getOperand(1).getReg() != SrcReg)
3342 return false;
3343 // Compare against zero.
3344 SrcReg2 = 0;
3345 CmpMask = ~0;
3346 CmpValue = 0;
3347 return true;
3348 }
3349 return false;
3350 }
3351
3352 /// Check whether the first instruction, whose only
3353 /// purpose is to update flags, can be made redundant.
3354 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3355 /// This function can be extended later on.
3356 /// SrcReg, SrcRegs: register operands for FlagI.
3357 /// ImmValue: immediate for FlagI if it takes an immediate.
3358 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3359 unsigned SrcReg, unsigned SrcReg2,
3360 int ImmMask, int ImmValue,
3361 const MachineInstr &OI) {
3362 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3363 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3364 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3365 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3366 ((OI.getOperand(1).getReg() == SrcReg &&
3367 OI.getOperand(2).getReg() == SrcReg2) ||
3368 (OI.getOperand(1).getReg() == SrcReg2 &&
3369 OI.getOperand(2).getReg() == SrcReg)))
3370 return true;
3371
3372 if (ImmMask != 0 &&
3373 ((FlagI.getOpcode() == X86::CMP64ri32 &&
3374 OI.getOpcode() == X86::SUB64ri32) ||
3375 (FlagI.getOpcode() == X86::CMP64ri8 &&
3376 OI.getOpcode() == X86::SUB64ri8) ||
3377 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3378 (FlagI.getOpcode() == X86::CMP32ri8 &&
3379 OI.getOpcode() == X86::SUB32ri8) ||
3380 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3381 (FlagI.getOpcode() == X86::CMP16ri8 &&
3382 OI.getOpcode() == X86::SUB16ri8) ||
3383 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3384 OI.getOperand(1).getReg() == SrcReg &&
3385 OI.getOperand(2).getImm() == ImmValue)
3386 return true;
3387 return false;
3388 }
3389
3390 /// Check whether the definition can be converted
3391 /// to remove a comparison against zero.
3392 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3393 NoSignFlag = false;
3394
3395 switch (MI.getOpcode()) {
3396 default: return false;
3397
3398 // The shift instructions only modify ZF if their shift count is non-zero.
3399 // N.B.: The processor truncates the shift count depending on the encoding.
3400 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
3401 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
3402 return getTruncatedShiftCount(MI, 2) != 0;
3403
3404 // Some left shift instructions can be turned into LEA instructions but only
3405 // if their flags aren't used. Avoid transforming such instructions.
3406 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
3407 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3408 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3409 return ShAmt != 0;
3410 }
3411
3412 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3413 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3414 return getTruncatedShiftCount(MI, 3) != 0;
3415
3416 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3417 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3418 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3419 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3420 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
3421 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3422 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3423 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3424 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3425 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3426 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
3427 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3428 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3429 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3430 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3431 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3432 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3433 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3434 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3435 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3436 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3437 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3438 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3439 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3440 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3441 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3442 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3443 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3444 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
3445 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
3446 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
3447 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
3448 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3449 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
3450 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
3451 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
3452 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:
3453 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
3454 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
3455 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
3456 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
3457 case X86::ANDN32rr: case X86::ANDN32rm:
3458 case X86::ANDN64rr: case X86::ANDN64rm:
3459 case X86::BLSI32rr: case X86::BLSI32rm:
3460 case X86::BLSI64rr: case X86::BLSI64rm:
3461 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3462 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3463 case X86::BLSR32rr: case X86::BLSR32rm:
3464 case X86::BLSR64rr: case X86::BLSR64rm:
3465 case X86::BZHI32rr: case X86::BZHI32rm:
3466 case X86::BZHI64rr: case X86::BZHI64rm:
3467 case X86::LZCNT16rr: case X86::LZCNT16rm:
3468 case X86::LZCNT32rr: case X86::LZCNT32rm:
3469 case X86::LZCNT64rr: case X86::LZCNT64rm:
3470 case X86::POPCNT16rr:case X86::POPCNT16rm:
3471 case X86::POPCNT32rr:case X86::POPCNT32rm:
3472 case X86::POPCNT64rr:case X86::POPCNT64rm:
3473 case X86::TZCNT16rr: case X86::TZCNT16rm:
3474 case X86::TZCNT32rr: case X86::TZCNT32rm:
3475 case X86::TZCNT64rr: case X86::TZCNT64rm:
3476 case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3477 case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3478 case X86::BLCI32rr: case X86::BLCI32rm:
3479 case X86::BLCI64rr: case X86::BLCI64rm:
3480 case X86::BLCIC32rr: case X86::BLCIC32rm:
3481 case X86::BLCIC64rr: case X86::BLCIC64rm:
3482 case X86::BLCMSK32rr: case X86::BLCMSK32rm:
3483 case X86::BLCMSK64rr: case X86::BLCMSK64rm:
3484 case X86::BLCS32rr: case X86::BLCS32rm:
3485 case X86::BLCS64rr: case X86::BLCS64rm:
3486 case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3487 case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3488 case X86::BLSIC32rr: case X86::BLSIC32rm:
3489 case X86::BLSIC64rr: case X86::BLSIC64rm:
3490 case X86::T1MSKC32rr: case X86::T1MSKC32rm:
3491 case X86::T1MSKC64rr: case X86::T1MSKC64rm:
3492 case X86::TZMSK32rr: case X86::TZMSK32rm:
3493 case X86::TZMSK64rr: case X86::TZMSK64rm:
3494 return true;
3495 case X86::BEXTR32rr: case X86::BEXTR64rr:
3496 case X86::BEXTR32rm: case X86::BEXTR64rm:
3497 case X86::BEXTRI32ri: case X86::BEXTRI32mi:
3498 case X86::BEXTRI64ri: case X86::BEXTRI64mi:
3499 // BEXTR doesn't update the sign flag so we can't use it.
3500 NoSignFlag = true;
3501 return true;
3502 }
3503 }
3504
3505 /// Check whether the use can be converted to remove a comparison against zero.
3506 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3507 switch (MI.getOpcode()) {
3508 default: return X86::COND_INVALID;
3509 case X86::NEG8r:
3510 case X86::NEG16r:
3511 case X86::NEG32r:
3512 case X86::NEG64r:
3513 return X86::COND_AE;
3514 case X86::LZCNT16rr:
3515 case X86::LZCNT32rr:
3516 case X86::LZCNT64rr:
3517 return X86::COND_B;
3518 case X86::POPCNT16rr:
3519 case X86::POPCNT32rr:
3520 case X86::POPCNT64rr:
3521 return X86::COND_E;
3522 case X86::TZCNT16rr:
3523 case X86::TZCNT32rr:
3524 case X86::TZCNT64rr:
3525 return X86::COND_B;
3526 case X86::BSF16rr:
3527 case X86::BSF32rr:
3528 case X86::BSF64rr:
3529 case X86::BSR16rr:
3530 case X86::BSR32rr:
3531 case X86::BSR64rr:
3532 return X86::COND_E;
3533 case X86::BLSI32rr:
3534 case X86::BLSI64rr:
3535 return X86::COND_AE;
3536 case X86::BLSR32rr:
3537 case X86::BLSR64rr:
3538 case X86::BLSMSK32rr:
3539 case X86::BLSMSK64rr:
3540 return X86::COND_B;
3541 // TODO: TBM instructions.
3542 }
3543 }
3544
3545 /// Check if there exists an earlier instruction that
3546 /// operates on the same source operands and sets flags in the same way as
3547 /// Compare; remove Compare if possible.
3548 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3549 unsigned SrcReg2, int CmpMask,
3550 int CmpValue,
3551 const MachineRegisterInfo *MRI) const {
3552 // Check whether we can replace SUB with CMP.
3553 switch (CmpInstr.getOpcode()) {
3554 default: break;
3555 case X86::SUB64ri32:
3556 case X86::SUB64ri8:
3557 case X86::SUB32ri:
3558 case X86::SUB32ri8:
3559 case X86::SUB16ri:
3560 case X86::SUB16ri8:
3561 case X86::SUB8ri:
3562 case X86::SUB64rm:
3563 case X86::SUB32rm:
3564 case X86::SUB16rm:
3565 case X86::SUB8rm:
3566 case X86::SUB64rr:
3567 case X86::SUB32rr:
3568 case X86::SUB16rr:
3569 case X86::SUB8rr: {
3570 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3571 return false;
3572 // There is no use of the destination register, we can replace SUB with CMP.
3573 unsigned NewOpcode = 0;
3574 switch (CmpInstr.getOpcode()) {
3575 default: llvm_unreachable("Unreachable!");
3576 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3577 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3578 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3579 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3580 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3581 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3582 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3583 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3584 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3585 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3586 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3587 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3588 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3589 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3590 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3591 }
3592 CmpInstr.setDesc(get(NewOpcode));
3593 CmpInstr.RemoveOperand(0);
3594 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3595 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3596 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3597 return false;
3598 }
3599 }
3600
3601 // Get the unique definition of SrcReg.
3602 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3603 if (!MI) return false;
3604
3605 // CmpInstr is the first instruction of the BB.
3606 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3607
3608 // If we are comparing against zero, check whether we can use MI to update
3609 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3610 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3611 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3612 return false;
3613
3614 // If we have a use of the source register between the def and our compare
3615 // instruction we can eliminate the compare iff the use sets EFLAGS in the
3616 // right way.
3617 bool ShouldUpdateCC = false;
3618 bool NoSignFlag = false;
3619 X86::CondCode NewCC = X86::COND_INVALID;
3620 if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3621 // Scan forward from the use until we hit the use we're looking for or the
3622 // compare instruction.
3623 for (MachineBasicBlock::iterator J = MI;; ++J) {
3624 // Do we have a convertible instruction?
3625 NewCC = isUseDefConvertible(*J);
3626 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3627 J->getOperand(1).getReg() == SrcReg) {
3628 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3629 ShouldUpdateCC = true; // Update CC later on.
3630 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3631 // with the new def.
3632 Def = J;
3633 MI = &*Def;
3634 break;
3635 }
3636
3637 if (J == I)
3638 return false;
3639 }
3640 }
3641
3642 // We are searching for an earlier instruction that can make CmpInstr
3643 // redundant and that instruction will be saved in Sub.
3644 MachineInstr *Sub = nullptr;
3645 const TargetRegisterInfo *TRI = &getRegisterInfo();
3646
3647 // We iterate backward, starting from the instruction before CmpInstr and
3648 // stop when reaching the definition of a source register or done with the BB.
3649 // RI points to the instruction before CmpInstr.
3650 // If the definition is in this basic block, RE points to the definition;
3651 // otherwise, RE is the rend of the basic block.
3652 MachineBasicBlock::reverse_iterator
3653 RI = ++I.getReverse(),
3654 RE = CmpInstr.getParent() == MI->getParent()
3655 ? Def.getReverse() /* points to MI */
3656 : CmpInstr.getParent()->rend();
3657 MachineInstr *Movr0Inst = nullptr;
3658 for (; RI != RE; ++RI) {
3659 MachineInstr &Instr = *RI;
3660 // Check whether CmpInstr can be made redundant by the current instruction.
3661 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3662 CmpValue, Instr)) {
3663 Sub = &Instr;
3664 break;
3665 }
3666
3667 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3668 Instr.readsRegister(X86::EFLAGS, TRI)) {
3669 // This instruction modifies or uses EFLAGS.
3670
3671 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3672 // They are safe to move up, if the definition to EFLAGS is dead and
3673 // earlier instructions do not read or write EFLAGS.
3674 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3675 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3676 Movr0Inst = &Instr;
3677 continue;
3678 }
3679
3680 // We can't remove CmpInstr.
3681 return false;
3682 }
3683 }
3684
3685 // Return false if no candidates exist.
3686 if (!IsCmpZero && !Sub)
3687 return false;
3688
3689 bool IsSwapped =
3690 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
3691 Sub->getOperand(2).getReg() == SrcReg);
3692
3693 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3694 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3695 // If we are done with the basic block, we need to check whether EFLAGS is
3696 // live-out.
3697 bool IsSafe = false;
3698 SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3699 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3700 for (++I; I != E; ++I) {
3701 const MachineInstr &Instr = *I;
3702 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3703 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3704 // We should check the usage if this instruction uses and updates EFLAGS.
3705 if (!UseEFLAGS && ModifyEFLAGS) {
3706 // It is safe to remove CmpInstr if EFLAGS is updated again.
3707 IsSafe = true;
3708 break;
3709 }
3710 if (!UseEFLAGS && !ModifyEFLAGS)
3711 continue;
3712
3713 // EFLAGS is used by this instruction.
3714 X86::CondCode OldCC = X86::COND_INVALID;
3715 if (IsCmpZero || IsSwapped) {
3716 // We decode the condition code from opcode.
3717 if (Instr.isBranch())
3718 OldCC = X86::getCondFromBranch(Instr);
3719 else {
3720 OldCC = X86::getCondFromSETCC(Instr);
3721 if (OldCC == X86::COND_INVALID)
3722 OldCC = X86::getCondFromCMov(Instr);
3723 }
3724 if (OldCC == X86::COND_INVALID) return false;
3725 }
3726 X86::CondCode ReplacementCC = X86::COND_INVALID;
3727 if (IsCmpZero) {
3728 switch (OldCC) {
3729 default: break;
3730 case X86::COND_A: case X86::COND_AE:
3731 case X86::COND_B: case X86::COND_BE:
3732 case X86::COND_G: case X86::COND_GE:
3733 case X86::COND_L: case X86::COND_LE:
3734 case X86::COND_O: case X86::COND_NO:
3735 // CF and OF are used, we can't perform this optimization.
3736 return false;
3737 case X86::COND_S: case X86::COND_NS:
3738 // If SF is used, but the instruction doesn't update the SF, then we
3739 // can't do the optimization.
3740 if (NoSignFlag)
3741 return false;
3742 break;
3743 }
3744
3745 // If we're updating the condition code check if we have to reverse the
3746 // condition.
3747 if (ShouldUpdateCC)
3748 switch (OldCC) {
3749 default:
3750 return false;
3751 case X86::COND_E:
3752 ReplacementCC = NewCC;
3753 break;
3754 case X86::COND_NE:
3755 ReplacementCC = GetOppositeBranchCondition(NewCC);
3756 break;
3757 }
3758 } else if (IsSwapped) {
3759 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3760 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3761 // We swap the condition code and synthesize the new opcode.
3762 ReplacementCC = getSwappedCondition(OldCC);
3763 if (ReplacementCC == X86::COND_INVALID) return false;
3764 }
3765
3766 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3767 // Push the MachineInstr to OpsToUpdate.
3768 // If it is safe to remove CmpInstr, the condition code of these
3769 // instructions will be modified.
3770 OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3771 }
3772 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3773 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3774 IsSafe = true;
3775 break;
3776 }
3777 }
3778
3779 // If EFLAGS is not killed nor re-defined, we should check whether it is
3780 // live-out. If it is live-out, do not optimize.
3781 if ((IsCmpZero || IsSwapped) && !IsSafe) {
3782 MachineBasicBlock *MBB = CmpInstr.getParent();
3783 for (MachineBasicBlock *Successor : MBB->successors())
3784 if (Successor->isLiveIn(X86::EFLAGS))
3785 return false;
3786 }
3787
3788 // The instruction to be updated is either Sub or MI.
3789 Sub = IsCmpZero ? MI : Sub;
3790 // Move Movr0Inst to the appropriate place before Sub.
3791 if (Movr0Inst) {
3792 // Look backwards until we find a def that doesn't use the current EFLAGS.
3793 Def = Sub;
3794 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3795 InsertE = Sub->getParent()->rend();
3796 for (; InsertI != InsertE; ++InsertI) {
3797 MachineInstr *Instr = &*InsertI;
3798 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3799 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3800 Sub->getParent()->remove(Movr0Inst);
3801 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3802 Movr0Inst);
3803 break;
3804 }
3805 }
3806 if (InsertI == InsertE)
3807 return false;
3808 }
3809
3810 // Make sure Sub instruction defines EFLAGS and mark the def live.
3811 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3812 assert(FlagDef && "Unable to locate a def EFLAGS operand");
3813 FlagDef->setIsDead(false);
3814
3815 CmpInstr.eraseFromParent();
3816
3817 // Modify the condition code of instructions in OpsToUpdate.
3818 for (auto &Op : OpsToUpdate) {
3819 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3820 .setImm(Op.second);
3821 }
3822 return true;
3823 }
3824
3825 /// Try to remove the load by folding it to a register
3826 /// operand at the use. We fold the load instructions if load defines a virtual
3827 /// register, the virtual register is used once in the same BB, and the
3828 /// instructions in-between do not load or store, and have no side effects.
3829 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3830 const MachineRegisterInfo *MRI,
3831 unsigned &FoldAsLoadDefReg,
3832 MachineInstr *&DefMI) const {
3833 // Check whether we can move DefMI here.
3834 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3835 assert(DefMI);
3836 bool SawStore = false;
3837 if (!DefMI->isSafeToMove(nullptr, SawStore))
3838 return nullptr;
3839
3840 // Collect information about virtual register operands of MI.
3841 SmallVector<unsigned, 1> SrcOperandIds;
3842 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3843 MachineOperand &MO = MI.getOperand(i);
3844 if (!MO.isReg())
3845 continue;
3846 Register Reg = MO.getReg();
3847 if (Reg != FoldAsLoadDefReg)
3848 continue;
3849 // Do not fold if we have a subreg use or a def.
3850 if (MO.getSubReg() || MO.isDef())
3851 return nullptr;
3852 SrcOperandIds.push_back(i);
3853 }
3854 if (SrcOperandIds.empty())
3855 return nullptr;
3856
3857 // Check whether we can fold the def into SrcOperandId.
3858 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3859 FoldAsLoadDefReg = 0;
3860 return FoldMI;
3861 }
3862
3863 return nullptr;
3864 }
3865
3866 /// Expand a single-def pseudo instruction to a two-addr
3867 /// instruction with two undef reads of the register being defined.
3868 /// This is used for mapping:
3869 /// %xmm4 = V_SET0
3870 /// to:
3871 /// %xmm4 = PXORrr undef %xmm4, undef %xmm4
3872 ///
3873 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3874 const MCInstrDesc &Desc) {
3875 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3876 Register Reg = MIB->getOperand(0).getReg();
3877 MIB->setDesc(Desc);
3878
3879 // MachineInstr::addOperand() will insert explicit operands before any
3880 // implicit operands.
3881 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3882 // But we don't trust that.
3883 assert(MIB->getOperand(1).getReg() == Reg &&
3884 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3885 return true;
3886 }
3887
3888 /// Expand a single-def pseudo instruction to a two-addr
3889 /// instruction with two %k0 reads.
3890 /// This is used for mapping:
3891 /// %k4 = K_SET1
3892 /// to:
3893 /// %k4 = KXNORrr %k0, %k0
3894 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3895 const MCInstrDesc &Desc, unsigned Reg) {
3896 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3897 MIB->setDesc(Desc);
3898 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3899 return true;
3900 }
3901
3902 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3903 bool MinusOne) {
3904 MachineBasicBlock &MBB = *MIB->getParent();
3905 DebugLoc DL = MIB->getDebugLoc();
3906 Register Reg = MIB->getOperand(0).getReg();
3907
3908 // Insert the XOR.
3909 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3910 .addReg(Reg, RegState::Undef)
3911 .addReg(Reg, RegState::Undef);
3912
3913 // Turn the pseudo into an INC or DEC.
3914 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3915 MIB.addReg(Reg);
3916
3917 return true;
3918 }
3919
3920 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3921 const TargetInstrInfo &TII,
3922 const X86Subtarget &Subtarget) {
3923 MachineBasicBlock &MBB = *MIB->getParent();
3924 DebugLoc DL = MIB->getDebugLoc();
3925 int64_t Imm = MIB->getOperand(1).getImm();
3926 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3927 MachineBasicBlock::iterator I = MIB.getInstr();
3928
3929 int StackAdjustment;
3930
3931 if (Subtarget.is64Bit()) {
3932 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3933 MIB->getOpcode() == X86::MOV32ImmSExti8);
3934
3935 // Can't use push/pop lowering if the function might write to the red zone.
3936 X86MachineFunctionInfo *X86FI =
3937 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3938 if (X86FI->getUsesRedZone()) {
3939 MIB->setDesc(TII.get(MIB->getOpcode() ==
3940 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3941 return true;
3942 }
3943
3944 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3945 // widen the register if necessary.
3946 StackAdjustment = 8;
3947 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3948 MIB->setDesc(TII.get(X86::POP64r));
3949 MIB->getOperand(0)
3950 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3951 } else {
3952 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3953 StackAdjustment = 4;
3954 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3955 MIB->setDesc(TII.get(X86::POP32r));
3956 }
3957
3958 // Build CFI if necessary.
3959 MachineFunction &MF = *MBB.getParent();
3960 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3961 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3962 bool NeedsDwarfCFI =
3963 !IsWin64Prologue &&
3964 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3965 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3966 if (EmitCFI) {
3967 TFL->BuildCFI(MBB, I, DL,
3968 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3969 TFL->BuildCFI(MBB, std::next(I), DL,
3970 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3971 }
3972
3973 return true;
3974 }
3975
3976 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3977 // code sequence is needed for other targets.
3978 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3979 const TargetInstrInfo &TII) {
3980 MachineBasicBlock &MBB = *MIB->getParent();
3981 DebugLoc DL = MIB->getDebugLoc();
3982 Register Reg = MIB->getOperand(0).getReg();
3983 const GlobalValue *GV =
3984 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3985 auto Flags = MachineMemOperand::MOLoad |
3986 MachineMemOperand::MODereferenceable |
3987 MachineMemOperand::MOInvariant;
3988 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3989 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3990 MachineBasicBlock::iterator I = MIB.getInstr();
3991
3992 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3993 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3994 .addMemOperand(MMO);
3995 MIB->setDebugLoc(DL);
3996 MIB->setDesc(TII.get(X86::MOV64rm));
3997 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3998 }
3999
4000 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4001 MachineBasicBlock &MBB = *MIB->getParent();
4002 MachineFunction &MF = *MBB.getParent();
4003 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4004 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4005 unsigned XorOp =
4006 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4007 MIB->setDesc(TII.get(XorOp));
4008 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4009 return true;
4010 }
4011
4012 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4013 // but not VLX. If it uses an extended register we need to use an instruction
4014 // that loads the lower 128/256-bit, but is available with only AVX512F.
4015 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4016 const TargetRegisterInfo *TRI,
4017 const MCInstrDesc &LoadDesc,
4018 const MCInstrDesc &BroadcastDesc,
4019 unsigned SubIdx) {
4020 Register DestReg = MIB->getOperand(0).getReg();
4021 // Check if DestReg is XMM16-31 or YMM16-31.
4022 if (TRI->getEncodingValue(DestReg) < 16) {
4023 // We can use a normal VEX encoded load.
4024 MIB->setDesc(LoadDesc);
4025 } else {
4026 // Use a 128/256-bit VBROADCAST instruction.
4027 MIB->setDesc(BroadcastDesc);
4028 // Change the destination to a 512-bit register.
4029 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4030 MIB->getOperand(0).setReg(DestReg);
4031 }
4032 return true;
4033 }
4034
4035 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4036 // but not VLX. If it uses an extended register we need to use an instruction
4037 // that stores the lower 128/256-bit, but is available with only AVX512F.
4038 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4039 const TargetRegisterInfo *TRI,
4040 const MCInstrDesc &StoreDesc,
4041 const MCInstrDesc &ExtractDesc,
4042 unsigned SubIdx) {
4043 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4044 // Check if DestReg is XMM16-31 or YMM16-31.
4045 if (TRI->getEncodingValue(SrcReg) < 16) {
4046 // We can use a normal VEX encoded store.
4047 MIB->setDesc(StoreDesc);
4048 } else {
4049 // Use a VEXTRACTF instruction.
4050 MIB->setDesc(ExtractDesc);
4051 // Change the destination to a 512-bit register.
4052 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4053 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4054 MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4055 }
4056
4057 return true;
4058 }
4059
4060 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4061 MIB->setDesc(Desc);
4062 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4063 // Temporarily remove the immediate so we can add another source register.
4064 MIB->RemoveOperand(2);
4065 // Add the register. Don't copy the kill flag if there is one.
4066 MIB.addReg(MIB->getOperand(1).getReg(),
4067 getUndefRegState(MIB->getOperand(1).isUndef()));
4068 // Add back the immediate.
4069 MIB.addImm(ShiftAmt);
4070 return true;
4071 }
4072
4073 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4074 bool HasAVX = Subtarget.hasAVX();
4075 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4076 switch (MI.getOpcode()) {
4077 case X86::MOV32r0:
4078 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4079 case X86::MOV32r1:
4080 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4081 case X86::MOV32r_1:
4082 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4083 case X86::MOV32ImmSExti8:
4084 case X86::MOV64ImmSExti8:
4085 return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4086 case X86::SETB_C8r:
4087 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4088 case X86::SETB_C16r:
4089 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4090 case X86::SETB_C32r:
4091 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4092 case X86::SETB_C64r:
4093 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4094 case X86::MMX_SET0:
4095 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4096 case X86::V_SET0:
4097 case X86::FsFLD0SS:
4098 case X86::FsFLD0SD:
4099 case X86::FsFLD0F128:
4100 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4101 case X86::AVX_SET0: {
4102 assert(HasAVX && "AVX not supported");
4103 const TargetRegisterInfo *TRI = &getRegisterInfo();
4104 Register SrcReg = MIB->getOperand(0).getReg();
4105 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4106 MIB->getOperand(0).setReg(XReg);
4107 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4108 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4109 return true;
4110 }
4111 case X86::AVX512_128_SET0:
4112 case X86::AVX512_FsFLD0SS:
4113 case X86::AVX512_FsFLD0SD:
4114 case X86::AVX512_FsFLD0F128: {
4115 bool HasVLX = Subtarget.hasVLX();
4116 Register SrcReg = MIB->getOperand(0).getReg();
4117 const TargetRegisterInfo *TRI = &getRegisterInfo();
4118 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4119 return Expand2AddrUndef(MIB,
4120 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4121 // Extended register without VLX. Use a larger XOR.
4122 SrcReg =
4123 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4124 MIB->getOperand(0).setReg(SrcReg);
4125 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4126 }
4127 case X86::AVX512_256_SET0:
4128 case X86::AVX512_512_SET0: {
4129 bool HasVLX = Subtarget.hasVLX();
4130 Register SrcReg = MIB->getOperand(0).getReg();
4131 const TargetRegisterInfo *TRI = &getRegisterInfo();
4132 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4133 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4134 MIB->getOperand(0).setReg(XReg);
4135 Expand2AddrUndef(MIB,
4136 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4137 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4138 return true;
4139 }
4140 if (MI.getOpcode() == X86::AVX512_256_SET0) {
4141 // No VLX so we must reference a zmm.
4142 unsigned ZReg =
4143 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4144 MIB->getOperand(0).setReg(ZReg);
4145 }
4146 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4147 }
4148 case X86::V_SETALLONES:
4149 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4150 case X86::AVX2_SETALLONES:
4151 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4152 case X86::AVX1_SETALLONES: {
4153 Register Reg = MIB->getOperand(0).getReg();
4154 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4155 MIB->setDesc(get(X86::VCMPPSYrri));
4156 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4157 return true;
4158 }
4159 case X86::AVX512_512_SETALLONES: {
4160 Register Reg = MIB->getOperand(0).getReg();
4161 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4162 // VPTERNLOGD needs 3 register inputs and an immediate.
4163 // 0xff will return 1s for any input.
4164 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4165 .addReg(Reg, RegState::Undef).addImm(0xff);
4166 return true;
4167 }
4168 case X86::AVX512_512_SEXT_MASK_32:
4169 case X86::AVX512_512_SEXT_MASK_64: {
4170 Register Reg = MIB->getOperand(0).getReg();
4171 Register MaskReg = MIB->getOperand(1).getReg();
4172 unsigned MaskState = getRegState(MIB->getOperand(1));
4173 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4174 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4175 MI.RemoveOperand(1);
4176 MIB->setDesc(get(Opc));
4177 // VPTERNLOG needs 3 register inputs and an immediate.
4178 // 0xff will return 1s for any input.
4179 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4180 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4181 return true;
4182 }
4183 case X86::VMOVAPSZ128rm_NOVLX:
4184 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4185 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4186 case X86::VMOVUPSZ128rm_NOVLX:
4187 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4188 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4189 case X86::VMOVAPSZ256rm_NOVLX:
4190 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4191 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4192 case X86::VMOVUPSZ256rm_NOVLX:
4193 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4194 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4195 case X86::VMOVAPSZ128mr_NOVLX:
4196 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4197 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4198 case X86::VMOVUPSZ128mr_NOVLX:
4199 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4200 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4201 case X86::VMOVAPSZ256mr_NOVLX:
4202 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4203 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4204 case X86::VMOVUPSZ256mr_NOVLX:
4205 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4206 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4207 case X86::MOV32ri64: {
4208 Register Reg = MIB->getOperand(0).getReg();
4209 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4210 MI.setDesc(get(X86::MOV32ri));
4211 MIB->getOperand(0).setReg(Reg32);
4212 MIB.addReg(Reg, RegState::ImplicitDefine);
4213 return true;
4214 }
4215
4216 // KNL does not recognize dependency-breaking idioms for mask registers,
4217 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4218 // Using %k0 as the undef input register is a performance heuristic based
4219 // on the assumption that %k0 is used less frequently than the other mask
4220 // registers, since it is not usable as a write mask.
4221 // FIXME: A more advanced approach would be to choose the best input mask
4222 // register based on context.
4223 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4224 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4225 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4226 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4227 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4228 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4229 case TargetOpcode::LOAD_STACK_GUARD:
4230 expandLoadStackGuard(MIB, *this);
4231 return true;
4232 case X86::XOR64_FP:
4233 case X86::XOR32_FP:
4234 return expandXorFP(MIB, *this);
4235 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4236 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4237 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4238 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4239 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4240 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4241 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4242 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4243 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4244 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4245 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4246 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4247 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4248 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4249 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4250 }
4251 return false;
4252 }
4253
4254 /// Return true for all instructions that only update
4255 /// the first 32 or 64-bits of the destination register and leave the rest
4256 /// unmodified. This can be used to avoid folding loads if the instructions
4257 /// only update part of the destination register, and the non-updated part is
4258 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4259 /// instructions breaks the partial register dependency and it can improve
4260 /// performance. e.g.:
4261 ///
4262 /// movss (%rdi), %xmm0
4263 /// cvtss2sd %xmm0, %xmm0
4264 ///
4265 /// Instead of
4266 /// cvtss2sd (%rdi), %xmm0
4267 ///
4268 /// FIXME: This should be turned into a TSFlags.
4269 ///
4270 static bool hasPartialRegUpdate(unsigned Opcode,
4271 const X86Subtarget &Subtarget,
4272 bool ForLoadFold = false) {
4273 switch (Opcode) {
4274 case X86::CVTSI2SSrr:
4275 case X86::CVTSI2SSrm:
4276 case X86::CVTSI642SSrr:
4277 case X86::CVTSI642SSrm:
4278 case X86::CVTSI2SDrr:
4279 case X86::CVTSI2SDrm:
4280 case X86::CVTSI642SDrr:
4281 case X86::CVTSI642SDrm:
4282 // Load folding won't effect the undef register update since the input is
4283 // a GPR.
4284 return !ForLoadFold;
4285 case X86::CVTSD2SSrr:
4286 case X86::CVTSD2SSrm:
4287 case X86::CVTSS2SDrr:
4288 case X86::CVTSS2SDrm:
4289 case X86::MOVHPDrm:
4290 case X86::MOVHPSrm:
4291 case X86::MOVLPDrm:
4292 case X86::MOVLPSrm:
4293 case X86::RCPSSr:
4294 case X86::RCPSSm:
4295 case X86::RCPSSr_Int:
4296 case X86::RCPSSm_Int:
4297 case X86::ROUNDSDr:
4298 case X86::ROUNDSDm:
4299 case X86::ROUNDSSr:
4300 case X86::ROUNDSSm:
4301 case X86::RSQRTSSr:
4302 case X86::RSQRTSSm:
4303 case X86::RSQRTSSr_Int:
4304 case X86::RSQRTSSm_Int:
4305 case X86::SQRTSSr:
4306 case X86::SQRTSSm:
4307 case X86::SQRTSSr_Int:
4308 case X86::SQRTSSm_Int:
4309 case X86::SQRTSDr:
4310 case X86::SQRTSDm:
4311 case X86::SQRTSDr_Int:
4312 case X86::SQRTSDm_Int:
4313 return true;
4314 // GPR
4315 case X86::POPCNT32rm:
4316 case X86::POPCNT32rr:
4317 case X86::POPCNT64rm:
4318 case X86::POPCNT64rr:
4319 return Subtarget.hasPOPCNTFalseDeps();
4320 case X86::LZCNT32rm:
4321 case X86::LZCNT32rr:
4322 case X86::LZCNT64rm:
4323 case X86::LZCNT64rr:
4324 case X86::TZCNT32rm:
4325 case X86::TZCNT32rr:
4326 case X86::TZCNT64rm:
4327 case X86::TZCNT64rr:
4328 return Subtarget.hasLZCNTFalseDeps();
4329 }
4330
4331 return false;
4332 }
4333
4334 /// Inform the BreakFalseDeps pass how many idle
4335 /// instructions we would like before a partial register update.
4336 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4337 const MachineInstr &MI, unsigned OpNum,
4338 const TargetRegisterInfo *TRI) const {
4339 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4340 return 0;
4341
4342 // If MI is marked as reading Reg, the partial register update is wanted.
4343 const MachineOperand &MO = MI.getOperand(0);
4344 Register Reg = MO.getReg();
4345 if (Register::isVirtualRegister(Reg)) {
4346 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4347 return 0;
4348 } else {
4349 if (MI.readsRegister(Reg, TRI))
4350 return 0;
4351 }
4352
4353 // If any instructions in the clearance range are reading Reg, insert a
4354 // dependency breaking instruction, which is inexpensive and is likely to
4355 // be hidden in other instruction's cycles.
4356 return PartialRegUpdateClearance;
4357 }
4358
4359 // Return true for any instruction the copies the high bits of the first source
4360 // operand into the unused high bits of the destination operand.
4361 static bool hasUndefRegUpdate(unsigned Opcode, unsigned &OpNum,
4362 bool ForLoadFold = false) {
4363 // Set the OpNum parameter to the first source operand.
4364 OpNum = 1;
4365 switch (Opcode) {
4366 case X86::VCVTSI2SSrr:
4367 case X86::VCVTSI2SSrm:
4368 case X86::VCVTSI2SSrr_Int:
4369 case X86::VCVTSI2SSrm_Int:
4370 case X86::VCVTSI642SSrr:
4371 case X86::VCVTSI642SSrm:
4372 case X86::VCVTSI642SSrr_Int:
4373 case X86::VCVTSI642SSrm_Int:
4374 case X86::VCVTSI2SDrr:
4375 case X86::VCVTSI2SDrm:
4376 case X86::VCVTSI2SDrr_Int:
4377 case X86::VCVTSI2SDrm_Int:
4378 case X86::VCVTSI642SDrr:
4379 case X86::VCVTSI642SDrm:
4380 case X86::VCVTSI642SDrr_Int:
4381 case X86::VCVTSI642SDrm_Int:
4382 // AVX-512
4383 case X86::VCVTSI2SSZrr:
4384 case X86::VCVTSI2SSZrm:
4385 case X86::VCVTSI2SSZrr_Int:
4386 case X86::VCVTSI2SSZrrb_Int:
4387 case X86::VCVTSI2SSZrm_Int:
4388 case X86::VCVTSI642SSZrr:
4389 case X86::VCVTSI642SSZrm:
4390 case X86::VCVTSI642SSZrr_Int:
4391 case X86::VCVTSI642SSZrrb_Int:
4392 case X86::VCVTSI642SSZrm_Int:
4393 case X86::VCVTSI2SDZrr:
4394 case X86::VCVTSI2SDZrm:
4395 case X86::VCVTSI2SDZrr_Int:
4396 case X86::VCVTSI2SDZrm_Int:
4397 case X86::VCVTSI642SDZrr:
4398 case X86::VCVTSI642SDZrm:
4399 case X86::VCVTSI642SDZrr_Int:
4400 case X86::VCVTSI642SDZrrb_Int:
4401 case X86::VCVTSI642SDZrm_Int:
4402 case X86::VCVTUSI2SSZrr:
4403 case X86::VCVTUSI2SSZrm:
4404 case X86::VCVTUSI2SSZrr_Int:
4405 case X86::VCVTUSI2SSZrrb_Int:
4406 case X86::VCVTUSI2SSZrm_Int:
4407 case X86::VCVTUSI642SSZrr:
4408 case X86::VCVTUSI642SSZrm:
4409 case X86::VCVTUSI642SSZrr_Int:
4410 case X86::VCVTUSI642SSZrrb_Int:
4411 case X86::VCVTUSI642SSZrm_Int:
4412 case X86::VCVTUSI2SDZrr:
4413 case X86::VCVTUSI2SDZrm:
4414 case X86::VCVTUSI2SDZrr_Int:
4415 case X86::VCVTUSI2SDZrm_Int:
4416 case X86::VCVTUSI642SDZrr:
4417 case X86::VCVTUSI642SDZrm:
4418 case X86::VCVTUSI642SDZrr_Int:
4419 case X86::VCVTUSI642SDZrrb_Int:
4420 case X86::VCVTUSI642SDZrm_Int:
4421 // Load folding won't effect the undef register update since the input is
4422 // a GPR.
4423 return !ForLoadFold;
4424 case X86::VCVTSD2SSrr:
4425 case X86::VCVTSD2SSrm:
4426 case X86::VCVTSD2SSrr_Int:
4427 case X86::VCVTSD2SSrm_Int:
4428 case X86::VCVTSS2SDrr:
4429 case X86::VCVTSS2SDrm:
4430 case X86::VCVTSS2SDrr_Int:
4431 case X86::VCVTSS2SDrm_Int:
4432 case X86::VRCPSSr:
4433 case X86::VRCPSSr_Int:
4434 case X86::VRCPSSm:
4435 case X86::VRCPSSm_Int:
4436 case X86::VROUNDSDr:
4437 case X86::VROUNDSDm:
4438 case X86::VROUNDSDr_Int:
4439 case X86::VROUNDSDm_Int:
4440 case X86::VROUNDSSr:
4441 case X86::VROUNDSSm:
4442 case X86::VROUNDSSr_Int:
4443 case X86::VROUNDSSm_Int:
4444 case X86::VRSQRTSSr:
4445 case X86::VRSQRTSSr_Int:
4446 case X86::VRSQRTSSm:
4447 case X86::VRSQRTSSm_Int:
4448 case X86::VSQRTSSr:
4449 case X86::VSQRTSSr_Int:
4450 case X86::VSQRTSSm:
4451 case X86::VSQRTSSm_Int:
4452 case X86::VSQRTSDr:
4453 case X86::VSQRTSDr_Int:
4454 case X86::VSQRTSDm:
4455 case X86::VSQRTSDm_Int:
4456 // AVX-512
4457 case X86::VCVTSD2SSZrr:
4458 case X86::VCVTSD2SSZrr_Int:
4459 case X86::VCVTSD2SSZrrb_Int:
4460 case X86::VCVTSD2SSZrm:
4461 case X86::VCVTSD2SSZrm_Int:
4462 case X86::VCVTSS2SDZrr:
4463 case X86::VCVTSS2SDZrr_Int:
4464 case X86::VCVTSS2SDZrrb_Int:
4465 case X86::VCVTSS2SDZrm:
4466 case X86::VCVTSS2SDZrm_Int:
4467 case X86::VGETEXPSDZr:
4468 case X86::VGETEXPSDZrb:
4469 case X86::VGETEXPSDZm:
4470 case X86::VGETEXPSSZr:
4471 case X86::VGETEXPSSZrb:
4472 case X86::VGETEXPSSZm:
4473 case X86::VGETMANTSDZrri:
4474 case X86::VGETMANTSDZrrib:
4475 case X86::VGETMANTSDZrmi:
4476 case X86::VGETMANTSSZrri:
4477 case X86::VGETMANTSSZrrib:
4478 case X86::VGETMANTSSZrmi:
4479 case X86::VRNDSCALESDZr:
4480 case X86::VRNDSCALESDZr_Int:
4481 case X86::VRNDSCALESDZrb_Int:
4482 case X86::VRNDSCALESDZm:
4483 case X86::VRNDSCALESDZm_Int:
4484 case X86::VRNDSCALESSZr:
4485 case X86::VRNDSCALESSZr_Int:
4486 case X86::VRNDSCALESSZrb_Int:
4487 case X86::VRNDSCALESSZm:
4488 case X86::VRNDSCALESSZm_Int:
4489 case X86::VRCP14SDZrr:
4490 case X86::VRCP14SDZrm:
4491 case X86::VRCP14SSZrr:
4492 case X86::VRCP14SSZrm:
4493 case X86::VRCP28SDZr:
4494 case X86::VRCP28SDZrb:
4495 case X86::VRCP28SDZm:
4496 case X86::VRCP28SSZr:
4497 case X86::VRCP28SSZrb:
4498 case X86::VRCP28SSZm:
4499 case X86::VREDUCESSZrmi:
4500 case X86::VREDUCESSZrri:
4501 case X86::VREDUCESSZrrib:
4502 case X86::VRSQRT14SDZrr:
4503 case X86::VRSQRT14SDZrm:
4504 case X86::VRSQRT14SSZrr:
4505 case X86::VRSQRT14SSZrm:
4506 case X86::VRSQRT28SDZr:
4507 case X86::VRSQRT28SDZrb:
4508 case X86::VRSQRT28SDZm:
4509 case X86::VRSQRT28SSZr:
4510 case X86::VRSQRT28SSZrb:
4511 case X86::VRSQRT28SSZm:
4512 case X86::VSQRTSSZr:
4513 case X86::VSQRTSSZr_Int:
4514 case X86::VSQRTSSZrb_Int:
4515 case X86::VSQRTSSZm:
4516 case X86::VSQRTSSZm_Int:
4517 case X86::VSQRTSDZr:
4518 case X86::VSQRTSDZr_Int:
4519 case X86::VSQRTSDZrb_Int:
4520 case X86::VSQRTSDZm:
4521 case X86::VSQRTSDZm_Int:
4522 return true;
4523 case X86::VMOVSSZrrk:
4524 case X86::VMOVSDZrrk:
4525 OpNum = 3;
4526 return true;
4527 case X86::VMOVSSZrrkz:
4528 case X86::VMOVSDZrrkz:
4529 OpNum = 2;
4530 return true;
4531 }
4532
4533 return false;
4534 }
4535
4536 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4537 /// before certain undef register reads.
4538 ///
4539 /// This catches the VCVTSI2SD family of instructions:
4540 ///
4541 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4542 ///
4543 /// We should to be careful *not* to catch VXOR idioms which are presumably
4544 /// handled specially in the pipeline:
4545 ///
4546 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4547 ///
4548 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4549 /// high bits that are passed-through are not live.
4550 unsigned
4551 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4552 const TargetRegisterInfo *TRI) const {
4553 if (!hasUndefRegUpdate(MI.getOpcode(), OpNum))
4554 return 0;
4555
4556 const MachineOperand &MO = MI.getOperand(OpNum);
4557 if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4558 return UndefRegClearance;
4559 }
4560 return 0;
4561 }
4562
4563 void X86InstrInfo::breakPartialRegDependency(
4564 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4565 Register Reg = MI.getOperand(OpNum).getReg();
4566 // If MI kills this register, the false dependence is already broken.
4567 if (MI.killsRegister(Reg, TRI))
4568 return;
4569
4570 if (X86::VR128RegClass.contains(Reg)) {
4571 // These instructions are all floating point domain, so xorps is the best
4572 // choice.
4573 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4574 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4575 .addReg(Reg, RegState::Undef)
4576 .addReg(Reg, RegState::Undef);
4577 MI.addRegisterKilled(Reg, TRI, true);
4578 } else if (X86::VR256RegClass.contains(Reg)) {
4579 // Use vxorps to clear the full ymm register.
4580 // It wants to read and write the xmm sub-register.
4581 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4582 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4583 .addReg(XReg, RegState::Undef)
4584 .addReg(XReg, RegState::Undef)
4585 .addReg(Reg, RegState::ImplicitDefine);
4586 MI.addRegisterKilled(Reg, TRI, true);
4587 } else if (X86::GR64RegClass.contains(Reg)) {
4588 // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4589 // as well.
4590 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4591 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4592 .addReg(XReg, RegState::Undef)
4593 .addReg(XReg, RegState::Undef)
4594 .addReg(Reg, RegState::ImplicitDefine);
4595 MI.addRegisterKilled(Reg, TRI, true);
4596 } else if (X86::GR32RegClass.contains(Reg)) {
4597 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4598 .addReg(Reg, RegState::Undef)
4599 .addReg(Reg, RegState::Undef);
4600 MI.addRegisterKilled(Reg, TRI, true);
4601 }
4602 }
4603
4604 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4605 int PtrOffset = 0) {
4606 unsigned NumAddrOps = MOs.size();
4607
4608 if (NumAddrOps < 4) {
4609 // FrameIndex only - add an immediate offset (whether its zero or not).
4610 for (unsigned i = 0; i != NumAddrOps; ++i)
4611 MIB.add(MOs[i]);
4612 addOffset(MIB, PtrOffset);
4613 } else {
4614 // General Memory Addressing - we need to add any offset to an existing
4615 // offset.
4616 assert(MOs.size() == 5 && "Unexpected memory operand list length");
4617 for (unsigned i = 0; i != NumAddrOps; ++i) {
4618 const MachineOperand &MO = MOs[i];
4619 if (i == 3 && PtrOffset != 0) {
4620 MIB.addDisp(MO, PtrOffset);
4621 } else {
4622 MIB.add(MO);
4623 }
4624 }
4625 }
4626 }
4627
4628 static void updateOperandRegConstraints(MachineFunction &MF,
4629 MachineInstr &NewMI,
4630 const TargetInstrInfo &TII) {
4631 MachineRegisterInfo &MRI = MF.getRegInfo();
4632 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4633
4634 for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4635 MachineOperand &MO = NewMI.getOperand(Idx);
4636 // We only need to update constraints on virtual register operands.
4637 if (!MO.isReg())
4638 continue;
4639 Register Reg = MO.getReg();
4640 if (!Register::isVirtualRegister(Reg))
4641 continue;
4642
4643 auto *NewRC = MRI.constrainRegClass(
4644 Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4645 if (!NewRC) {
4646 LLVM_DEBUG(
4647 dbgs() << "WARNING: Unable to update register constraint for operand "
4648 << Idx << " of instruction:\n";
4649 NewMI.dump(); dbgs() << "\n");
4650 }
4651 }
4652 }
4653
4654 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4655 ArrayRef<MachineOperand> MOs,
4656 MachineBasicBlock::iterator InsertPt,
4657 MachineInstr &MI,
4658 const TargetInstrInfo &TII) {
4659 // Create the base instruction with the memory operand as the first part.
4660 // Omit the implicit operands, something BuildMI can't do.
4661 MachineInstr *NewMI =
4662 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4663 MachineInstrBuilder MIB(MF, NewMI);
4664 addOperands(MIB, MOs);
4665
4666 // Loop over the rest of the ri operands, converting them over.
4667 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4668 for (unsigned i = 0; i != NumOps; ++i) {
4669 MachineOperand &MO = MI.getOperand(i + 2);
4670 MIB.add(MO);
4671 }
4672 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4673 MachineOperand &MO = MI.getOperand(i);
4674 MIB.add(MO);
4675 }
4676
4677 updateOperandRegConstraints(MF, *NewMI, TII);
4678
4679 MachineBasicBlock *MBB = InsertPt->getParent();
4680 MBB->insert(InsertPt, NewMI);
4681
4682 return MIB;
4683 }
4684
4685 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4686 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4687 MachineBasicBlock::iterator InsertPt,
4688 MachineInstr &MI, const TargetInstrInfo &TII,
4689 int PtrOffset = 0) {
4690 // Omit the implicit operands, something BuildMI can't do.
4691 MachineInstr *NewMI =
4692 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4693 MachineInstrBuilder MIB(MF, NewMI);
4694
4695 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4696 MachineOperand &MO = MI.getOperand(i);
4697 if (i == OpNo) {
4698 assert(MO.isReg() && "Expected to fold into reg operand!");
4699 addOperands(MIB, MOs, PtrOffset);
4700 } else {
4701 MIB.add(MO);
4702 }
4703 }
4704
4705 updateOperandRegConstraints(MF, *NewMI, TII);
4706
4707 MachineBasicBlock *MBB = InsertPt->getParent();
4708 MBB->insert(InsertPt, NewMI);
4709
4710 return MIB;
4711 }
4712
4713 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4714 ArrayRef<MachineOperand> MOs,
4715 MachineBasicBlock::iterator InsertPt,
4716 MachineInstr &MI) {
4717 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4718 MI.getDebugLoc(), TII.get(Opcode));
4719 addOperands(MIB, MOs);
4720 return MIB.addImm(0);
4721 }
4722
4723 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4724 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4725 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4726 unsigned Size, unsigned Align) const {
4727 switch (MI.getOpcode()) {
4728 case X86::INSERTPSrr:
4729 case X86::VINSERTPSrr:
4730 case X86::VINSERTPSZrr:
4731 // Attempt to convert the load of inserted vector into a fold load
4732 // of a single float.
4733 if (OpNum == 2) {
4734 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4735 unsigned ZMask = Imm & 15;
4736 unsigned DstIdx = (Imm >> 4) & 3;
4737 unsigned SrcIdx = (Imm >> 6) & 3;
4738
4739 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4740 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4741 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4742 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 4 <= Align) {
4743 int PtrOffset = SrcIdx * 4;
4744 unsigned NewImm = (DstIdx << 4) | ZMask;
4745 unsigned NewOpCode =
4746 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4747 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
4748 X86::INSERTPSrm;
4749 MachineInstr *NewMI =
4750 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4751 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4752 return NewMI;
4753 }
4754 }
4755 break;
4756 case X86::MOVHLPSrr:
4757 case X86::VMOVHLPSrr:
4758 case X86::VMOVHLPSZrr:
4759 // Move the upper 64-bits of the second operand to the lower 64-bits.
4760 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4761 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4762 if (OpNum == 2) {
4763 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4764 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4765 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4766 if ((Size == 0 || Size >= 16) && RCSize >= 16 && 8 <= Align) {
4767 unsigned NewOpCode =
4768 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4769 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
4770 X86::MOVLPSrm;
4771 MachineInstr *NewMI =
4772 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4773 return NewMI;
4774 }
4775 }
4776 break;
4777 case X86::UNPCKLPDrr:
4778 // If we won't be able to fold this to the memory form of UNPCKL, use
4779 // MOVHPD instead. Done as custom because we can't have this in the load
4780 // table twice.
4781 if (OpNum == 2) {
4782 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4783 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4784 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4785 if ((Size == 0 || Size >= 16) && RCSize >= 16 && Align < 16) {
4786 MachineInstr *NewMI =
4787 FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
4788 return NewMI;
4789 }
4790 }
4791 break;
4792 }
4793
4794 return nullptr;
4795 }
4796
4797 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4798 MachineInstr &MI) {
4799 unsigned Ignored;
4800 if (!hasUndefRegUpdate(MI.getOpcode(), Ignored, /*ForLoadFold*/true) ||
4801 !MI.getOperand(1).isReg())
4802 return false;
4803
4804 // The are two cases we need to handle depending on where in the pipeline
4805 // the folding attempt is being made.
4806 // -Register has the undef flag set.
4807 // -Register is produced by the IMPLICIT_DEF instruction.
4808
4809 if (MI.getOperand(1).isUndef())
4810 return true;
4811
4812 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4813 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4814 return VRegDef && VRegDef->isImplicitDef();
4815 }
4816
4817
4818 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4819 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4820 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4821 unsigned Size, unsigned Align, bool AllowCommute) const {
4822 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4823 bool isTwoAddrFold = false;
4824
4825 // For CPUs that favor the register form of a call or push,
4826 // do not fold loads into calls or pushes, unless optimizing for size
4827 // aggressively.
4828 if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4829 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4830 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4831 MI.getOpcode() == X86::PUSH64r))
4832 return nullptr;
4833
4834 // Avoid partial and undef register update stalls unless optimizing for size.
4835 if (!MF.getFunction().hasOptSize() &&
4836 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4837 shouldPreventUndefRegUpdateMemFold(MF, MI)))
4838 return nullptr;
4839
4840 unsigned NumOps = MI.getDesc().getNumOperands();
4841 bool isTwoAddr =
4842 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4843
4844 // FIXME: AsmPrinter doesn't know how to handle
4845 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4846 if (MI.getOpcode() == X86::ADD32ri &&
4847 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4848 return nullptr;
4849
4850 // GOTTPOFF relocation loads can only be folded into add instructions.
4851 // FIXME: Need to exclude other relocations that only support specific
4852 // instructions.
4853 if (MOs.size() == X86::AddrNumOperands &&
4854 MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4855 MI.getOpcode() != X86::ADD64rr)
4856 return nullptr;
4857
4858 MachineInstr *NewMI = nullptr;
4859
4860 // Attempt to fold any custom cases we have.
4861 if (MachineInstr *CustomMI =
4862 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4863 return CustomMI;
4864
4865 const X86MemoryFoldTableEntry *I = nullptr;
4866
4867 // Folding a memory location into the two-address part of a two-address
4868 // instruction is different than folding it other places. It requires
4869 // replacing the *two* registers with the memory location.
4870 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4871 MI.getOperand(1).isReg() &&
4872 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4873 I = lookupTwoAddrFoldTable(MI.getOpcode());
4874 isTwoAddrFold = true;
4875 } else {
4876 if (OpNum == 0) {
4877 if (MI.getOpcode() == X86::MOV32r0) {
4878 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4879 if (NewMI)
4880 return NewMI;
4881 }
4882 }
4883
4884 I = lookupFoldTable(MI.getOpcode(), OpNum);
4885 }
4886
4887 if (I != nullptr) {
4888 unsigned Opcode = I->DstOp;
4889 unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4890 MinAlign = MinAlign ? 1 << (MinAlign - 1) : 0;
4891 if (Align < MinAlign)
4892 return nullptr;
4893 bool NarrowToMOV32rm = false;
4894 if (Size) {
4895 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4896 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4897 &RI, MF);
4898 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4899 if (Size < RCSize) {
4900 // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
4901 // Check if it's safe to fold the load. If the size of the object is
4902 // narrower than the load width, then it's not.
4903 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4904 return nullptr;
4905 // If this is a 64-bit load, but the spill slot is 32, then we can do
4906 // a 32-bit load which is implicitly zero-extended. This likely is
4907 // due to live interval analysis remat'ing a load from stack slot.
4908 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4909 return nullptr;
4910 Opcode = X86::MOV32rm;
4911 NarrowToMOV32rm = true;
4912 }
4913 }
4914
4915 if (isTwoAddrFold)
4916 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4917 else
4918 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4919
4920 if (NarrowToMOV32rm) {
4921 // If this is the special case where we use a MOV32rm to load a 32-bit
4922 // value and zero-extend the top bits. Change the destination register
4923 // to a 32-bit one.
4924 Register DstReg = NewMI->getOperand(0).getReg();
4925 if (Register::isPhysicalRegister(DstReg))
4926 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4927 else
4928 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4929 }
4930 return NewMI;
4931 }
4932
4933 // If the instruction and target operand are commutable, commute the
4934 // instruction and try again.
4935 if (AllowCommute) {
4936 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4937 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4938 bool HasDef = MI.getDesc().getNumDefs();
4939 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4940 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4941 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4942 bool Tied1 =
4943 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4944 bool Tied2 =
4945 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4946
4947 // If either of the commutable operands are tied to the destination
4948 // then we can not commute + fold.
4949 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4950 (HasDef && Reg0 == Reg2 && Tied2))
4951 return nullptr;
4952
4953 MachineInstr *CommutedMI =
4954 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4955 if (!CommutedMI) {
4956 // Unable to commute.
4957 return nullptr;
4958 }
4959 if (CommutedMI != &MI) {
4960 // New instruction. We can't fold from this.
4961 CommutedMI->eraseFromParent();
4962 return nullptr;
4963 }
4964
4965 // Attempt to fold with the commuted version of the instruction.
4966 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4967 Size, Align, /*AllowCommute=*/false);
4968 if (NewMI)
4969 return NewMI;
4970
4971 // Folding failed again - undo the commute before returning.
4972 MachineInstr *UncommutedMI =
4973 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4974 if (!UncommutedMI) {
4975 // Unable to commute.
4976 return nullptr;
4977 }
4978 if (UncommutedMI != &MI) {
4979 // New instruction. It doesn't need to be kept.
4980 UncommutedMI->eraseFromParent();
4981 return nullptr;
4982 }
4983
4984 // Return here to prevent duplicate fuse failure report.
4985 return nullptr;
4986 }
4987 }
4988
4989 // No fusion
4990 if (PrintFailedFusing && !MI.isCopy())
4991 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4992 return nullptr;
4993 }
4994
4995 MachineInstr *
4996 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4997 ArrayRef<unsigned> Ops,
4998 MachineBasicBlock::iterator InsertPt,
4999 int FrameIndex, LiveIntervals *LIS,
5000 VirtRegMap *VRM) const {
5001 // Check switch flag
5002 if (NoFusing)
5003 return nullptr;
5004
5005 // Avoid partial and undef register update stalls unless optimizing for size.
5006 if (!MF.getFunction().hasOptSize() &&
5007 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5008 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5009 return nullptr;
5010
5011 // Don't fold subreg spills, or reloads that use a high subreg.
5012 for (auto Op : Ops) {
5013 MachineOperand &MO = MI.getOperand(Op);
5014 auto SubReg = MO.getSubReg();
5015 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5016 return nullptr;
5017 }
5018
5019 const MachineFrameInfo &MFI = MF.getFrameInfo();
5020 unsigned Size = MFI.getObjectSize(FrameIndex);
5021 unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
5022 // If the function stack isn't realigned we don't want to fold instructions
5023 // that need increased alignment.
5024 if (!RI.needsStackRealignment(MF))
5025 Alignment =
5026 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5027 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5028 unsigned NewOpc = 0;
5029 unsigned RCSize = 0;
5030 switch (MI.getOpcode()) {
5031 default: return nullptr;
5032 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5033 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5034 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5035 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5036 }
5037 // Check if it's safe to fold the load. If the size of the object is
5038 // narrower than the load width, then it's not.
5039 if (Size < RCSize)
5040 return nullptr;
5041 // Change to CMPXXri r, 0 first.
5042 MI.setDesc(get(NewOpc));
5043 MI.getOperand(1).ChangeToImmediate(0);
5044 } else if (Ops.size() != 1)
5045 return nullptr;
5046
5047 return foldMemoryOperandImpl(MF, MI, Ops[0],
5048 MachineOperand::CreateFI(FrameIndex), InsertPt,
5049 Size, Alignment, /*AllowCommute=*/true);
5050 }
5051
5052 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5053 /// because the latter uses contents that wouldn't be defined in the folded
5054 /// version. For instance, this transformation isn't legal:
5055 /// movss (%rdi), %xmm0
5056 /// addps %xmm0, %xmm0
5057 /// ->
5058 /// addps (%rdi), %xmm0
5059 ///
5060 /// But this one is:
5061 /// movss (%rdi), %xmm0
5062 /// addss %xmm0, %xmm0
5063 /// ->
5064 /// addss (%rdi), %xmm0
5065 ///
5066 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5067 const MachineInstr &UserMI,
5068 const MachineFunction &MF) {
5069 unsigned Opc = LoadMI.getOpcode();
5070 unsigned UserOpc = UserMI.getOpcode();
5071 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5072 const TargetRegisterClass *RC =
5073 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5074 unsigned RegSize = TRI.getRegSizeInBits(*RC);
5075
5076 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5077 Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5078 Opc == X86::VMOVSSZrm_alt) &&
5079 RegSize > 32) {
5080 // These instructions only load 32 bits, we can't fold them if the
5081 // destination register is wider than 32 bits (4 bytes), and its user
5082 // instruction isn't scalar (SS).
5083 switch (UserOpc) {
5084 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5085 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5086 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5087 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5088 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5089 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5090 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5091 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5092 case X86::VCMPSSZrr_Intk:
5093 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5094 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5095 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5096 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5097 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5098 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int:
5099 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int:
5100 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int:
5101 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int:
5102 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int:
5103 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int:
5104 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int:
5105 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int:
5106 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5107 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5108 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5109 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5110 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5111 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5112 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5113 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5114 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5115 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5116 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5117 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5118 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5119 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5120 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5121 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5122 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5123 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5124 return false;
5125 default:
5126 return true;
5127 }
5128 }
5129
5130 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5131 Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5132 Opc == X86::VMOVSDZrm_alt) &&
5133 RegSize > 64) {
5134 // These instructions only load 64 bits, we can't fold them if the
5135 // destination register is wider than 64 bits (8 bytes), and its user
5136 // instruction isn't scalar (SD).
5137 switch (UserOpc) {
5138 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5139 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5140 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5141 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5142 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5143 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5144 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5145 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5146 case X86::VCMPSDZrr_Intk:
5147 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5148 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5149 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5150 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5151 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5152 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int:
5153 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int:
5154 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int:
5155 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int:
5156 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int:
5157 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int:
5158 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int:
5159 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int:
5160 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5161 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5162 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5163 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5164 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5165 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5166 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5167 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5168 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5169 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5170 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5171 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5172 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5173 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5174 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5175 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5176 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5177 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5178 return false;
5179 default:
5180 return true;
5181 }
5182 }
5183
5184 return false;
5185 }
5186
5187 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5188 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5189 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5190 LiveIntervals *LIS) const {
5191
5192 // TODO: Support the case where LoadMI loads a wide register, but MI
5193 // only uses a subreg.
5194 for (auto Op : Ops) {
5195 if (MI.getOperand(Op).getSubReg())
5196 return nullptr;
5197 }
5198
5199 // If loading from a FrameIndex, fold directly from the FrameIndex.
5200 unsigned NumOps = LoadMI.getDesc().getNumOperands();
5201 int FrameIndex;
5202 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5203 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5204 return nullptr;
5205 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5206 }
5207
5208 // Check switch flag
5209 if (NoFusing) return nullptr;
5210
5211 // Avoid partial and undef register update stalls unless optimizing for size.
5212 if (!MF.getFunction().hasOptSize() &&
5213 (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5214 shouldPreventUndefRegUpdateMemFold(MF, MI)))
5215 return nullptr;
5216
5217 // Determine the alignment of the load.
5218 unsigned Alignment = 0;
5219 if (LoadMI.hasOneMemOperand())
5220 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5221 else
5222 switch (LoadMI.getOpcode()) {
5223 case X86::AVX512_512_SET0:
5224 case X86::AVX512_512_SETALLONES:
5225 Alignment = 64;
5226 break;
5227 case X86::AVX2_SETALLONES:
5228 case X86::AVX1_SETALLONES:
5229 case X86::AVX_SET0:
5230 case X86::AVX512_256_SET0:
5231 Alignment = 32;
5232 break;
5233 case X86::V_SET0:
5234 case X86::V_SETALLONES:
5235 case X86::AVX512_128_SET0:
5236 case X86::FsFLD0F128:
5237 case X86::AVX512_FsFLD0F128:
5238 Alignment = 16;
5239 break;
5240 case X86::MMX_SET0:
5241 case X86::FsFLD0SD:
5242 case X86::AVX512_FsFLD0SD:
5243 Alignment = 8;
5244 break;
5245 case X86::FsFLD0SS:
5246 case X86::AVX512_FsFLD0SS:
5247 Alignment = 4;
5248 break;
5249 default:
5250 return nullptr;
5251 }
5252 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5253 unsigned NewOpc = 0;
5254 switch (MI.getOpcode()) {
5255 default: return nullptr;
5256 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
5257 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5258 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5259 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5260 }
5261 // Change to CMPXXri r, 0 first.
5262 MI.setDesc(get(NewOpc));
5263 MI.getOperand(1).ChangeToImmediate(0);
5264 } else if (Ops.size() != 1)
5265 return nullptr;
5266
5267 // Make sure the subregisters match.
5268 // Otherwise we risk changing the size of the load.
5269 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5270 return nullptr;
5271
5272 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5273 switch (LoadMI.getOpcode()) {
5274 case X86::MMX_SET0:
5275 case X86::V_SET0:
5276 case X86::V_SETALLONES:
5277 case X86::AVX2_SETALLONES:
5278 case X86::AVX1_SETALLONES:
5279 case X86::AVX_SET0:
5280 case X86::AVX512_128_SET0:
5281 case X86::AVX512_256_SET0:
5282 case X86::AVX512_512_SET0:
5283 case X86::AVX512_512_SETALLONES:
5284 case X86::FsFLD0SD:
5285 case X86::AVX512_FsFLD0SD:
5286 case X86::FsFLD0SS:
5287 case X86::AVX512_FsFLD0SS:
5288 case X86::FsFLD0F128:
5289 case X86::AVX512_FsFLD0F128: {
5290 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5291 // Create a constant-pool entry and operands to load from it.
5292
5293 // Medium and large mode can't fold loads this way.
5294 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5295 MF.getTarget().getCodeModel() != CodeModel::Kernel)
5296 return nullptr;
5297
5298 // x86-32 PIC requires a PIC base register for constant pools.
5299 unsigned PICBase = 0;
5300 if (MF.getTarget().isPositionIndependent()) {
5301 if (Subtarget.is64Bit())
5302 PICBase = X86::RIP;
5303 else
5304 // FIXME: PICBase = getGlobalBaseReg(&MF);
5305 // This doesn't work for several reasons.
5306 // 1. GlobalBaseReg may have been spilled.
5307 // 2. It may not be live at MI.
5308 return nullptr;
5309 }
5310
5311 // Create a constant-pool entry.
5312 MachineConstantPool &MCP = *MF.getConstantPool();
5313 Type *Ty;
5314 unsigned Opc = LoadMI.getOpcode();
5315 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5316 Ty = Type::getFloatTy(MF.getFunction().getContext());
5317 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5318 Ty = Type::getDoubleTy(MF.getFunction().getContext());
5319 else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
5320 Ty = Type::getFP128Ty(MF.getFunction().getContext());
5321 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5322 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5323 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5324 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5325 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5326 else if (Opc == X86::MMX_SET0)
5327 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5328 else
5329 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5330
5331 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5332 Opc == X86::AVX512_512_SETALLONES ||
5333 Opc == X86::AVX1_SETALLONES);
5334 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5335 Constant::getNullValue(Ty);
5336 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5337
5338 // Create operands to load from the constant pool entry.
5339 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5340 MOs.push_back(MachineOperand::CreateImm(1));
5341 MOs.push_back(MachineOperand::CreateReg(0, false));
5342 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5343 MOs.push_back(MachineOperand::CreateReg(0, false));
5344 break;
5345 }
5346 default: {
5347 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5348 return nullptr;
5349
5350 // Folding a normal load. Just copy the load's address operands.
5351 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5352 LoadMI.operands_begin() + NumOps);
5353 break;
5354 }
5355 }
5356 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5357 /*Size=*/0, Alignment, /*AllowCommute=*/true);
5358 }
5359
5360 static SmallVector<MachineMemOperand *, 2>
5361 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5362 SmallVector<MachineMemOperand *, 2> LoadMMOs;
5363
5364 for (MachineMemOperand *MMO : MMOs) {
5365 if (!MMO->isLoad())
5366 continue;
5367
5368 if (!MMO->isStore()) {
5369 // Reuse the MMO.
5370 LoadMMOs.push_back(MMO);
5371 } else {
5372 // Clone the MMO and unset the store flag.
5373 LoadMMOs.push_back(MF.getMachineMemOperand(
5374 MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5375 }
5376 }
5377
5378 return LoadMMOs;
5379 }
5380
5381 static SmallVector<MachineMemOperand *, 2>
5382 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5383 SmallVector<MachineMemOperand *, 2> StoreMMOs;
5384
5385 for (MachineMemOperand *MMO : MMOs) {
5386 if (!MMO->isStore())
5387 continue;
5388
5389 if (!MMO->isLoad()) {
5390 // Reuse the MMO.
5391 StoreMMOs.push_back(MMO);
5392 } else {
5393 // Clone the MMO and unset the load flag.
5394 StoreMMOs.push_back(MF.getMachineMemOperand(
5395 MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5396 }
5397 }
5398
5399 return StoreMMOs;
5400 }
5401
5402 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
5403 const TargetRegisterClass *RC,
5404 const X86Subtarget &STI) {
5405 assert(STI.hasAVX512() && "Expected at least AVX512!");
5406 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
5407 assert((SpillSize == 64 || STI.hasVLX()) &&
5408 "Can't broadcast less than 64 bytes without AVX512VL!");
5409
5410 switch (I->Flags & TB_BCAST_MASK) {
5411 default: llvm_unreachable("Unexpected broadcast type!");
5412 case TB_BCAST_D:
5413 switch (SpillSize) {
5414 default: llvm_unreachable("Unknown spill size");
5415 case 16: return X86::VPBROADCASTDZ128m;
5416 case 32: return X86::VPBROADCASTDZ256m;
5417 case 64: return X86::VPBROADCASTDZm;
5418 }
5419 break;
5420 case TB_BCAST_Q:
5421 switch (SpillSize) {
5422 default: llvm_unreachable("Unknown spill size");
5423 case 16: return X86::VPBROADCASTQZ128m;
5424 case 32: return X86::VPBROADCASTQZ256m;
5425 case 64: return X86::VPBROADCASTQZm;
5426 }
5427 break;
5428 case TB_BCAST_SS:
5429 switch (SpillSize) {
5430 default: llvm_unreachable("Unknown spill size");
5431 case 16: return X86::VBROADCASTSSZ128m;
5432 case 32: return X86::VBROADCASTSSZ256m;
5433 case 64: return X86::VBROADCASTSSZm;
5434 }
5435 break;
5436 case TB_BCAST_SD:
5437 switch (SpillSize) {
5438 default: llvm_unreachable("Unknown spill size");
5439 case 16: return X86::VMOVDDUPZ128rm;
5440 case 32: return X86::VBROADCASTSDZ256m;
5441 case 64: return X86::VBROADCASTSDZm;
5442 }
5443 break;
5444 }
5445 }
5446
5447 bool X86InstrInfo::unfoldMemoryOperand(
5448 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5449 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5450 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5451 if (I == nullptr)
5452 return false;
5453 unsigned Opc = I->DstOp;
5454 unsigned Index = I->Flags & TB_INDEX_MASK;
5455 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5456 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5457 bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
5458 if (UnfoldLoad && !FoldedLoad)
5459 return false;
5460 UnfoldLoad &= FoldedLoad;
5461 if (UnfoldStore && !FoldedStore)
5462 return false;
5463 UnfoldStore &= FoldedStore;
5464
5465 const MCInstrDesc &MCID = get(Opc);
5466
5467 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5468 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5469 // TODO: Check if 32-byte or greater accesses are slow too?
5470 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5471 Subtarget.isUnalignedMem16Slow())
5472 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5473 // conservatively assume the address is unaligned. That's bad for
5474 // performance.
5475 return false;
5476 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5477 SmallVector<MachineOperand,2> BeforeOps;
5478 SmallVector<MachineOperand,2> AfterOps;
5479 SmallVector<MachineOperand,4> ImpOps;
5480 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5481 MachineOperand &Op = MI.getOperand(i);
5482 if (i >= Index && i < Index + X86::AddrNumOperands)
5483 AddrOps.push_back(Op);
5484 else if (Op.isReg() && Op.isImplicit())
5485 ImpOps.push_back(Op);
5486 else if (i < Index)
5487 BeforeOps.push_back(Op);
5488 else if (i > Index)
5489 AfterOps.push_back(Op);
5490 }
5491
5492 // Emit the load or broadcast instruction.
5493 if (UnfoldLoad) {
5494 auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5495
5496 unsigned Opc;
5497 if (FoldedBCast) {
5498 Opc = getBroadcastOpcode(I, RC, Subtarget);
5499 } else {
5500 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5501 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5502 Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
5503 }
5504
5505 DebugLoc DL;
5506 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
5507 for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
5508 MIB.add(AddrOps[i]);
5509 MIB.setMemRefs(MMOs);
5510 NewMIs.push_back(MIB);
5511
5512 if (UnfoldStore) {
5513 // Address operands cannot be marked isKill.
5514 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5515 MachineOperand &MO = NewMIs[0]->getOperand(i);
5516 if (MO.isReg())
5517 MO.setIsKill(false);
5518 }
5519 }
5520 }
5521
5522 // Emit the data processing instruction.
5523 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5524 MachineInstrBuilder MIB(MF, DataMI);
5525
5526 if (FoldedStore)
5527 MIB.addReg(Reg, RegState::Define);
5528 for (MachineOperand &BeforeOp : BeforeOps)
5529 MIB.add(BeforeOp);
5530 if (FoldedLoad)
5531 MIB.addReg(Reg);
5532 for (MachineOperand &AfterOp : AfterOps)
5533 MIB.add(AfterOp);
5534 for (MachineOperand &ImpOp : ImpOps) {
5535 MIB.addReg(ImpOp.getReg(),
5536 getDefRegState(ImpOp.isDef()) |
5537 RegState::Implicit |
5538 getKillRegState(ImpOp.isKill()) |
5539 getDeadRegState(ImpOp.isDead()) |
5540 getUndefRegState(ImpOp.isUndef()));
5541 }
5542 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5543 switch (DataMI->getOpcode()) {
5544 default: break;
5545 case X86::CMP64ri32:
5546 case X86::CMP64ri8:
5547 case X86::CMP32ri:
5548 case X86::CMP32ri8:
5549 case X86::CMP16ri:
5550 case X86::CMP16ri8:
5551 case X86::CMP8ri: {
5552 MachineOperand &MO0 = DataMI->getOperand(0);
5553 MachineOperand &MO1 = DataMI->getOperand(1);
5554 if (MO1.getImm() == 0) {
5555 unsigned NewOpc;
5556 switch (DataMI->getOpcode()) {
5557 default: llvm_unreachable("Unreachable!");
5558 case X86::CMP64ri8:
5559 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5560 case X86::CMP32ri8:
5561 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
5562 case X86::CMP16ri8:
5563 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5564 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5565 }
5566 DataMI->setDesc(get(NewOpc));
5567 MO1.ChangeToRegister(MO0.getReg(), false);
5568 }
5569 }
5570 }
5571 NewMIs.push_back(DataMI);
5572
5573 // Emit the store instruction.
5574 if (UnfoldStore) {
5575 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5576 auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5577 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
5578 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5579 unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
5580 DebugLoc DL;
5581 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
5582 for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
5583 MIB.add(AddrOps[i]);
5584 MIB.addReg(Reg, RegState::Kill);
5585 MIB.setMemRefs(MMOs);
5586 NewMIs.push_back(MIB);
5587 }
5588
5589 return true;
5590 }
5591
5592 bool
5593 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5594 SmallVectorImpl<SDNode*> &NewNodes) const {
5595 if (!N->isMachineOpcode())
5596 return false;
5597
5598 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5599 if (I == nullptr)
5600 return false;
5601 unsigned Opc = I->DstOp;
5602 unsigned Index = I->Flags & TB_INDEX_MASK;
5603 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5604 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5605 bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
5606 const MCInstrDesc &MCID = get(Opc);
5607 MachineFunction &MF = DAG.getMachineFunction();
5608 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5609 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5610 unsigned NumDefs = MCID.NumDefs;
5611 std::vector<SDValue> AddrOps;
5612 std::vector<SDValue> BeforeOps;
5613 std::vector<SDValue> AfterOps;
5614 SDLoc dl(N);
5615 unsigned NumOps = N->getNumOperands();
5616 for (unsigned i = 0; i != NumOps-1; ++i) {
5617 SDValue Op = N->getOperand(i);
5618 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5619 AddrOps.push_back(Op);
5620 else if (i < Index-NumDefs)
5621 BeforeOps.push_back(Op);
5622 else if (i > Index-NumDefs)
5623 AfterOps.push_back(Op);
5624 }
5625 SDValue Chain = N->getOperand(NumOps-1);
5626 AddrOps.push_back(Chain);
5627
5628 // Emit the load instruction.
5629 SDNode *Load = nullptr;
5630 if (FoldedLoad) {
5631 EVT VT = *TRI.legalclasstypes_begin(*RC);
5632 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5633 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5634 Subtarget.isUnalignedMem16Slow())
5635 // Do not introduce a slow unaligned load.
5636 return false;
5637 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5638 // memory access is slow above.
5639
5640 unsigned Opc;
5641 if (FoldedBCast) {
5642 Opc = getBroadcastOpcode(I, RC, Subtarget);
5643 } else {
5644 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5645 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5646 Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
5647 }
5648
5649 Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
5650 NewNodes.push_back(Load);
5651
5652 // Preserve memory reference information.
5653 DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5654 }
5655
5656 // Emit the data processing instruction.
5657 std::vector<EVT> VTs;
5658 const TargetRegisterClass *DstRC = nullptr;
5659 if (MCID.getNumDefs() > 0) {
5660 DstRC = getRegClass(MCID, 0, &RI, MF);
5661 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5662 }
5663 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5664 EVT VT = N->getValueType(i);
5665 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5666 VTs.push_back(VT);
5667 }
5668 if (Load)
5669 BeforeOps.push_back(SDValue(Load, 0));
5670 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5671 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5672 switch (Opc) {
5673 default: break;
5674 case X86::CMP64ri32:
5675 case X86::CMP64ri8:
5676 case X86::CMP32ri:
5677 case X86::CMP32ri8:
5678 case X86::CMP16ri:
5679 case X86::CMP16ri8:
5680 case X86::CMP8ri:
5681 if (isNullConstant(BeforeOps[1])) {
5682 switch (Opc) {
5683 default: llvm_unreachable("Unreachable!");
5684 case X86::CMP64ri8:
5685 case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5686 case X86::CMP32ri8:
5687 case X86::CMP32ri: Opc = X86::TEST32rr; break;
5688 case X86::CMP16ri8:
5689 case X86::CMP16ri: Opc = X86::TEST16rr; break;
5690 case X86::CMP8ri: Opc = X86::TEST8rr; break;
5691 }
5692 BeforeOps[1] = BeforeOps[0];
5693 }
5694 }
5695 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5696 NewNodes.push_back(NewNode);
5697
5698 // Emit the store instruction.
5699 if (FoldedStore) {
5700 AddrOps.pop_back();
5701 AddrOps.push_back(SDValue(NewNode, 0));
5702 AddrOps.push_back(Chain);
5703 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5704 if (MMOs.empty() && RC == &X86::VR128RegClass &&
5705 Subtarget.isUnalignedMem16Slow())
5706 // Do not introduce a slow unaligned store.
5707 return false;
5708 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5709 // memory access is slow above.
5710 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5711 bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5712 SDNode *Store =
5713 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5714 dl, MVT::Other, AddrOps);
5715 NewNodes.push_back(Store);
5716
5717 // Preserve memory reference information.
5718 DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5719 }
5720
5721 return true;
5722 }
5723
5724 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5725 bool UnfoldLoad, bool UnfoldStore,
5726 unsigned *LoadRegIndex) const {
5727 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5728 if (I == nullptr)
5729 return 0;
5730 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5731 bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5732 if (UnfoldLoad && !FoldedLoad)
5733 return 0;
5734 if (UnfoldStore && !FoldedStore)
5735 return 0;
5736 if (LoadRegIndex)
5737 *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5738 return I->DstOp;
5739 }
5740
5741 bool
5742 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5743 int64_t &Offset1, int64_t &Offset2) const {
5744 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5745 return false;
5746 unsigned Opc1 = Load1->getMachineOpcode();
5747 unsigned Opc2 = Load2->getMachineOpcode();
5748 switch (Opc1) {
5749 default: return false;
5750 case X86::MOV8rm:
5751 case X86::MOV16rm:
5752 case X86::MOV32rm:
5753 case X86::MOV64rm:
5754 case X86::LD_Fp32m:
5755 case X86::LD_Fp64m:
5756 case X86::LD_Fp80m:
5757 case X86::MOVSSrm:
5758 case X86::MOVSSrm_alt:
5759 case X86::MOVSDrm:
5760 case X86::MOVSDrm_alt:
5761 case X86::MMX_MOVD64rm:
5762 case X86::MMX_MOVQ64rm:
5763 case X86::MOVAPSrm:
5764 case X86::MOVUPSrm:
5765 case X86::MOVAPDrm:
5766 case X86::MOVUPDrm:
5767 case X86::MOVDQArm:
5768 case X86::MOVDQUrm:
5769 // AVX load instructions
5770 case X86::VMOVSSrm:
5771 case X86::VMOVSSrm_alt:
5772 case X86::VMOVSDrm:
5773 case X86::VMOVSDrm_alt:
5774 case X86::VMOVAPSrm:
5775 case X86::VMOVUPSrm:
5776 case X86::VMOVAPDrm:
5777 case X86::VMOVUPDrm:
5778 case X86::VMOVDQArm:
5779 case X86::VMOVDQUrm:
5780 case X86::VMOVAPSYrm:
5781 case X86::VMOVUPSYrm:
5782 case X86::VMOVAPDYrm:
5783 case X86::VMOVUPDYrm:
5784 case X86::VMOVDQAYrm:
5785 case X86::VMOVDQUYrm:
5786 // AVX512 load instructions
5787 case X86::VMOVSSZrm:
5788 case X86::VMOVSSZrm_alt:
5789 case X86::VMOVSDZrm:
5790 case X86::VMOVSDZrm_alt:
5791 case X86::VMOVAPSZ128rm:
5792 case X86::VMOVUPSZ128rm:
5793 case X86::VMOVAPSZ128rm_NOVLX:
5794 case X86::VMOVUPSZ128rm_NOVLX:
5795 case X86::VMOVAPDZ128rm:
5796 case X86::VMOVUPDZ128rm:
5797 case X86::VMOVDQU8Z128rm:
5798 case X86::VMOVDQU16Z128rm:
5799 case X86::VMOVDQA32Z128rm:
5800 case X86::VMOVDQU32Z128rm:
5801 case X86::VMOVDQA64Z128rm:
5802 case X86::VMOVDQU64Z128rm:
5803 case X86::VMOVAPSZ256rm:
5804 case X86::VMOVUPSZ256rm:
5805 case X86::VMOVAPSZ256rm_NOVLX:
5806 case X86::VMOVUPSZ256rm_NOVLX:
5807 case X86::VMOVAPDZ256rm:
5808 case X86::VMOVUPDZ256rm:
5809 case X86::VMOVDQU8Z256rm:
5810 case X86::VMOVDQU16Z256rm:
5811 case X86::VMOVDQA32Z256rm:
5812 case X86::VMOVDQU32Z256rm:
5813 case X86::VMOVDQA64Z256rm:
5814 case X86::VMOVDQU64Z256rm:
5815 case X86::VMOVAPSZrm:
5816 case X86::VMOVUPSZrm:
5817 case X86::VMOVAPDZrm:
5818 case X86::VMOVUPDZrm:
5819 case X86::VMOVDQU8Zrm:
5820 case X86::VMOVDQU16Zrm:
5821 case X86::VMOVDQA32Zrm:
5822 case X86::VMOVDQU32Zrm:
5823 case X86::VMOVDQA64Zrm:
5824 case X86::VMOVDQU64Zrm:
5825 case X86::KMOVBkm:
5826 case X86::KMOVWkm:
5827 case X86::KMOVDkm:
5828 case X86::KMOVQkm:
5829 break;
5830 }
5831 switch (Opc2) {
5832 default: return false;
5833 case X86::MOV8rm:
5834 case X86::MOV16rm:
5835 case X86::MOV32rm:
5836 case X86::MOV64rm:
5837 case X86::LD_Fp32m:
5838 case X86::LD_Fp64m:
5839 case X86::LD_Fp80m:
5840 case X86::MOVSSrm:
5841 case X86::MOVSSrm_alt:
5842 case X86::MOVSDrm:
5843 case X86::MOVSDrm_alt:
5844 case X86::MMX_MOVD64rm:
5845 case X86::MMX_MOVQ64rm:
5846 case X86::MOVAPSrm:
5847 case X86::MOVUPSrm:
5848 case X86::MOVAPDrm:
5849 case X86::MOVUPDrm:
5850 case X86::MOVDQArm:
5851 case X86::MOVDQUrm:
5852 // AVX load instructions
5853 case X86::VMOVSSrm:
5854 case X86::VMOVSSrm_alt:
5855 case X86::VMOVSDrm:
5856 case X86::VMOVSDrm_alt:
5857 case X86::VMOVAPSrm:
5858 case X86::VMOVUPSrm:
5859 case X86::VMOVAPDrm:
5860 case X86::VMOVUPDrm:
5861 case X86::VMOVDQArm:
5862 case X86::VMOVDQUrm:
5863 case X86::VMOVAPSYrm:
5864 case X86::VMOVUPSYrm:
5865 case X86::VMOVAPDYrm:
5866 case X86::VMOVUPDYrm:
5867 case X86::VMOVDQAYrm:
5868 case X86::VMOVDQUYrm:
5869 // AVX512 load instructions
5870 case X86::VMOVSSZrm:
5871 case X86::VMOVSSZrm_alt:
5872 case X86::VMOVSDZrm:
5873 case X86::VMOVSDZrm_alt:
5874 case X86::VMOVAPSZ128rm:
5875 case X86::VMOVUPSZ128rm:
5876 case X86::VMOVAPSZ128rm_NOVLX:
5877 case X86::VMOVUPSZ128rm_NOVLX:
5878 case X86::VMOVAPDZ128rm:
5879 case X86::VMOVUPDZ128rm:
5880 case X86::VMOVDQU8Z128rm:
5881 case X86::VMOVDQU16Z128rm:
5882 case X86::VMOVDQA32Z128rm:
5883 case X86::VMOVDQU32Z128rm:
5884 case X86::VMOVDQA64Z128rm:
5885 case X86::VMOVDQU64Z128rm:
5886 case X86::VMOVAPSZ256rm:
5887 case X86::VMOVUPSZ256rm:
5888 case X86::VMOVAPSZ256rm_NOVLX:
5889 case X86::VMOVUPSZ256rm_NOVLX:
5890 case X86::VMOVAPDZ256rm:
5891 case X86::VMOVUPDZ256rm:
5892 case X86::VMOVDQU8Z256rm:
5893 case X86::VMOVDQU16Z256rm:
5894 case X86::VMOVDQA32Z256rm:
5895 case X86::VMOVDQU32Z256rm:
5896 case X86::VMOVDQA64Z256rm:
5897 case X86::VMOVDQU64Z256rm:
5898 case X86::VMOVAPSZrm:
5899 case X86::VMOVUPSZrm:
5900 case X86::VMOVAPDZrm:
5901 case X86::VMOVUPDZrm:
5902 case X86::VMOVDQU8Zrm:
5903 case X86::VMOVDQU16Zrm:
5904 case X86::VMOVDQA32Zrm:
5905 case X86::VMOVDQU32Zrm:
5906 case X86::VMOVDQA64Zrm:
5907 case X86::VMOVDQU64Zrm:
5908 case X86::KMOVBkm:
5909 case X86::KMOVWkm:
5910 case X86::KMOVDkm:
5911 case X86::KMOVQkm:
5912 break;
5913 }
5914
5915 // Lambda to check if both the loads have the same value for an operand index.
5916 auto HasSameOp = [&](int I) {
5917 return Load1->getOperand(I) == Load2->getOperand(I);
5918 };
5919
5920 // All operands except the displacement should match.
5921 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5922 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5923 return false;
5924
5925 // Chain Operand must be the same.
5926 if (!HasSameOp(5))
5927 return false;
5928
5929 // Now let's examine if the displacements are constants.
5930 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5931 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5932 if (!Disp1 || !Disp2)
5933 return false;
5934
5935 Offset1 = Disp1->getSExtValue();
5936 Offset2 = Disp2->getSExtValue();
5937 return true;
5938 }
5939
5940 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5941 int64_t Offset1, int64_t Offset2,
5942 unsigned NumLoads) const {
5943 assert(Offset2 > Offset1);
5944 if ((Offset2 - Offset1) / 8 > 64)
5945 return false;
5946
5947 unsigned Opc1 = Load1->getMachineOpcode();
5948 unsigned Opc2 = Load2->getMachineOpcode();
5949 if (Opc1 != Opc2)
5950 return false; // FIXME: overly conservative?
5951
5952 switch (Opc1) {
5953 default: break;
5954 case X86::LD_Fp32m:
5955 case X86::LD_Fp64m:
5956 case X86::LD_Fp80m:
5957 case X86::MMX_MOVD64rm:
5958 case X86::MMX_MOVQ64rm:
5959 return false;
5960 }
5961
5962 EVT VT = Load1->getValueType(0);
5963 switch (VT.getSimpleVT().SimpleTy) {
5964 default:
5965 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5966 // have 16 of them to play with.
5967 if (Subtarget.is64Bit()) {
5968 if (NumLoads >= 3)
5969 return false;
5970 } else if (NumLoads) {
5971 return false;
5972 }
5973 break;
5974 case MVT::i8:
5975 case MVT::i16:
5976 case MVT::i32:
5977 case MVT::i64:
5978 case MVT::f32:
5979 case MVT::f64:
5980 if (NumLoads)
5981 return false;
5982 break;
5983 }
5984
5985 return true;
5986 }
5987
5988 bool X86InstrInfo::
5989 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5990 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5991 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5992 Cond[0].setImm(GetOppositeBranchCondition(CC));
5993 return false;
5994 }
5995
5996 bool X86InstrInfo::
5997 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5998 // FIXME: Return false for x87 stack register classes for now. We can't
5999 // allow any loads of these registers before FpGet_ST0_80.
6000 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6001 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6002 RC == &X86::RFP80RegClass);
6003 }
6004
6005 /// Return a virtual register initialized with the
6006 /// the global base register value. Output instructions required to
6007 /// initialize the register in the function entry block, if necessary.
6008 ///
6009 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6010 ///
6011 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6012 assert((!Subtarget.is64Bit() ||
6013 MF->getTarget().getCodeModel() == CodeModel::Medium ||
6014 MF->getTarget().getCodeModel() == CodeModel::Large) &&
6015 "X86-64 PIC uses RIP relative addressing");
6016
6017 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6018 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6019 if (GlobalBaseReg != 0)
6020 return GlobalBaseReg;
6021
6022 // Create the register. The code to initialize it is inserted
6023 // later, by the CGBR pass (below).
6024 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6025 GlobalBaseReg = RegInfo.createVirtualRegister(
6026 Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6027 X86FI->setGlobalBaseReg(GlobalBaseReg);
6028 return GlobalBaseReg;
6029 }
6030
6031 // These are the replaceable SSE instructions. Some of these have Int variants
6032 // that we don't include here. We don't want to replace instructions selected
6033 // by intrinsics.
6034 static const uint16_t ReplaceableInstrs[][3] = {
6035 //PackedSingle PackedDouble PackedInt
6036 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6037 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6038 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6039 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6040 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
6041 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
6042 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr },
6043 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
6044 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
6045 { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6046 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
6047 { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6048 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6049 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6050 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6051 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6052 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6053 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6054 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6055 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6056 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
6057 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6058 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6059 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6060 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6061 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6062 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6063 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6064 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6065 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6066 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6067 // AVX 128-bit support
6068 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6069 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6070 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6071 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6072 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
6073 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
6074 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr },
6075 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
6076 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
6077 { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6078 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
6079 { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6080 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6081 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6082 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6083 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6084 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6085 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6086 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
6087 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6088 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
6089 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6090 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6091 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6092 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6093 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6094 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6095 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6096 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6097 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6098 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6099 // AVX 256-bit support
6100 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6101 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6102 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6103 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6104 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
6105 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
6106 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm },
6107 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr },
6108 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi },
6109 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri },
6110 // AVX512 support
6111 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
6112 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6113 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6114 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
6115 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
6116 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
6117 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
6118 { X86::VMOVSDZrm_alt, X86::VMOVSDZrm_alt, X86::VMOVQI2PQIZrm },
6119 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
6120 { X86::VMOVSSZrm_alt, X86::VMOVSSZrm_alt, X86::VMOVDI2PDIZrm },
6121 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
6122 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
6123 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
6124 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
6125 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
6126 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
6127 { X86::VMOVDDUPZ128rr, X86::VMOVDDUPZ128rr, X86::VPBROADCASTQZ128r },
6128 { X86::VMOVDDUPZ128rm, X86::VMOVDDUPZ128rm, X86::VPBROADCASTQZ128m },
6129 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
6130 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
6131 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
6132 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
6133 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr },
6134 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm },
6135 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr },
6136 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm },
6137 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr },
6138 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm },
6139 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr },
6140 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm },
6141 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6142 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6143 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6144 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6145 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr },
6146 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr },
6147 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr },
6148 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr },
6149 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr },
6150 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr },
6151 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr },
6152 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr },
6153 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6154 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6155 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6156 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6157 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi },
6158 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri },
6159 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi },
6160 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri },
6161 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi },
6162 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri },
6163 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi },
6164 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri },
6165 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm },
6166 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr },
6167 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi },
6168 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri },
6169 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm },
6170 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr },
6171 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm },
6172 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr },
6173 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi },
6174 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri },
6175 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm },
6176 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr },
6177 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm },
6178 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr },
6179 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm },
6180 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr },
6181 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm },
6182 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr },
6183 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm },
6184 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr },
6185 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm },
6186 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr },
6187 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm },
6188 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr },
6189 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm },
6190 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr },
6191 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm },
6192 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr },
6193 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm },
6194 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr },
6195 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm },
6196 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr },
6197 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm },
6198 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr },
6199 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm },
6200 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr },
6201 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr },
6202 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr },
6203 };
6204
6205 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6206 //PackedSingle PackedDouble PackedInt
6207 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6208 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6209 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6210 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6211 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6212 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6213 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
6214 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6215 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
6216 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6217 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6218 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6219 { X86::VMOVDDUPrm, X86::VMOVDDUPrm, X86::VPBROADCASTQrm},
6220 { X86::VMOVDDUPrr, X86::VMOVDDUPrr, X86::VPBROADCASTQrr},
6221 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6222 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6223 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6224 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6225 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
6226 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri },
6227 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi },
6228 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi },
6229 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri },
6230 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm },
6231 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr },
6232 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm },
6233 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr },
6234 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm },
6235 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr },
6236 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm },
6237 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr },
6238 };
6239
6240 static const uint16_t ReplaceableInstrsFP[][3] = {
6241 //PackedSingle PackedDouble
6242 { X86::MOVLPSrm, X86::MOVLPDrm, X86::INSTRUCTION_LIST_END },
6243 { X86::MOVHPSrm, X86::MOVHPDrm, X86::INSTRUCTION_LIST_END },
6244 { X86::MOVHPSmr, X86::MOVHPDmr, X86::INSTRUCTION_LIST_END },
6245 { X86::VMOVLPSrm, X86::VMOVLPDrm, X86::INSTRUCTION_LIST_END },
6246 { X86::VMOVHPSrm, X86::VMOVHPDrm, X86::INSTRUCTION_LIST_END },
6247 { X86::VMOVHPSmr, X86::VMOVHPDmr, X86::INSTRUCTION_LIST_END },
6248 { X86::VMOVLPSZ128rm, X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6249 { X86::VMOVHPSZ128rm, X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6250 { X86::VMOVHPSZ128mr, X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6251 };
6252
6253 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6254 //PackedSingle PackedDouble PackedInt
6255 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6256 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6257 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6258 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6259 };
6260
6261 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6262 // Two integer columns for 64-bit and 32-bit elements.
6263 //PackedSingle PackedDouble PackedInt PackedInt
6264 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
6265 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
6266 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
6267 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
6268 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
6269 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
6270 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
6271 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
6272 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
6273 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
6274 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
6275 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
6276 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
6277 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
6278 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
6279 };
6280
6281 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6282 // Two integer columns for 64-bit and 32-bit elements.
6283 //PackedSingle PackedDouble PackedInt PackedInt
6284 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6285 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6286 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6287 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6288 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6289 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6290 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6291 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6292 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6293 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6294 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6295 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6296 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6297 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6298 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6299 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6300 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
6301 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
6302 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
6303 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
6304 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
6305 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
6306 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
6307 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
6308 };
6309
6310 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6311 // Two integer columns for 64-bit and 32-bit elements.
6312 //PackedSingle PackedDouble
6313 //PackedInt PackedInt
6314 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
6315 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
6316 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6317 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6318 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
6319 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
6320 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6321 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6322 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
6323 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
6324 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
6325 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
6326 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
6327 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
6328 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
6329 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
6330 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
6331 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
6332 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
6333 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
6334 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
6335 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
6336 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
6337 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
6338 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
6339 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
6340 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
6341 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
6342 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
6343 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
6344 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
6345 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
6346 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
6347 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
6348 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6349 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6350 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
6351 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
6352 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6353 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6354 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
6355 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
6356 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
6357 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
6358 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
6359 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
6360 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
6361 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
6362 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
6363 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
6364 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
6365 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
6366 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
6367 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
6368 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
6369 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
6370 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
6371 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
6372 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
6373 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
6374 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
6375 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
6376 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
6377 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
6378 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
6379 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
6380 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
6381 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
6382 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
6383 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
6384 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
6385 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
6386 { X86::VANDPSZrmk, X86::VANDPDZrmk,
6387 X86::VPANDQZrmk, X86::VPANDDZrmk },
6388 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
6389 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
6390 { X86::VANDPSZrrk, X86::VANDPDZrrk,
6391 X86::VPANDQZrrk, X86::VPANDDZrrk },
6392 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
6393 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
6394 { X86::VORPSZrmk, X86::VORPDZrmk,
6395 X86::VPORQZrmk, X86::VPORDZrmk },
6396 { X86::VORPSZrmkz, X86::VORPDZrmkz,
6397 X86::VPORQZrmkz, X86::VPORDZrmkz },
6398 { X86::VORPSZrrk, X86::VORPDZrrk,
6399 X86::VPORQZrrk, X86::VPORDZrrk },
6400 { X86::VORPSZrrkz, X86::VORPDZrrkz,
6401 X86::VPORQZrrkz, X86::VPORDZrrkz },
6402 { X86::VXORPSZrmk, X86::VXORPDZrmk,
6403 X86::VPXORQZrmk, X86::VPXORDZrmk },
6404 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
6405 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
6406 { X86::VXORPSZrrk, X86::VXORPDZrrk,
6407 X86::VPXORQZrrk, X86::VPXORDZrrk },
6408 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
6409 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
6410 // Broadcast loads can be handled the same as masked operations to avoid
6411 // changing element size.
6412 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
6413 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
6414 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
6415 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
6416 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
6417 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
6418 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
6419 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
6420 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
6421 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
6422 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
6423 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
6424 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
6425 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
6426 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
6427 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
6428 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
6429 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
6430 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6431 X86::VPANDQZrmb, X86::VPANDDZrmb },
6432 { X86::VANDPSZrmb, X86::VANDPDZrmb,
6433 X86::VPANDQZrmb, X86::VPANDDZrmb },
6434 { X86::VORPSZrmb, X86::VORPDZrmb,
6435 X86::VPORQZrmb, X86::VPORDZrmb },
6436 { X86::VXORPSZrmb, X86::VXORPDZrmb,
6437 X86::VPXORQZrmb, X86::VPXORDZrmb },
6438 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6439 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6440 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
6441 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
6442 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
6443 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
6444 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
6445 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
6446 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6447 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6448 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
6449 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
6450 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
6451 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
6452 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
6453 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
6454 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
6455 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
6456 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6457 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6458 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
6459 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
6460 { X86::VORPSZrmbk, X86::VORPDZrmbk,
6461 X86::VPORQZrmbk, X86::VPORDZrmbk },
6462 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
6463 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
6464 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6465 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6466 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6467 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6468 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
6469 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
6470 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6471 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6472 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6473 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6474 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6475 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6476 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
6477 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
6478 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6479 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6480 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
6481 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
6482 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6483 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6484 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
6485 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
6486 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
6487 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
6488 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
6489 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
6490 };
6491
6492 // NOTE: These should only be used by the custom domain methods.
6493 static const uint16_t ReplaceableBlendInstrs[][3] = {
6494 //PackedSingle PackedDouble PackedInt
6495 { X86::BLENDPSrmi, X86::BLENDPDrmi, X86::PBLENDWrmi },
6496 { X86::BLENDPSrri, X86::BLENDPDrri, X86::PBLENDWrri },
6497 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDWrmi },
6498 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDWrri },
6499 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDWYrmi },
6500 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDWYrri },
6501 };
6502 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
6503 //PackedSingle PackedDouble PackedInt
6504 { X86::VBLENDPSrmi, X86::VBLENDPDrmi, X86::VPBLENDDrmi },
6505 { X86::VBLENDPSrri, X86::VBLENDPDrri, X86::VPBLENDDrri },
6506 { X86::VBLENDPSYrmi, X86::VBLENDPDYrmi, X86::VPBLENDDYrmi },
6507 { X86::VBLENDPSYrri, X86::VBLENDPDYrri, X86::VPBLENDDYrri },
6508 };
6509
6510 // Special table for changing EVEX logic instructions to VEX.
6511 // TODO: Should we run EVEX->VEX earlier?
6512 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6513 // Two integer columns for 64-bit and 32-bit elements.
6514 //PackedSingle PackedDouble PackedInt PackedInt
6515 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6516 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6517 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
6518 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
6519 { X86::VORPSrm, X86::VORPDrm, X86::VPORQZ128rm, X86::VPORDZ128rm },
6520 { X86::VORPSrr, X86::VORPDrr, X86::VPORQZ128rr, X86::VPORDZ128rr },
6521 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
6522 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
6523 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6524 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6525 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
6526 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
6527 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORQZ256rm, X86::VPORDZ256rm },
6528 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORQZ256rr, X86::VPORDZ256rr },
6529 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
6530 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
6531 };
6532
6533 // FIXME: Some shuffle and unpack instructions have equivalents in different
6534 // domains, but they require a bit more work than just switching opcodes.
6535
6536 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6537 ArrayRef<uint16_t[3]> Table) {
6538 for (const uint16_t (&Row)[3] : Table)
6539 if (Row[domain-1] == opcode)
6540 return Row;
6541 return nullptr;
6542 }
6543
6544 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6545 ArrayRef<uint16_t[4]> Table) {
6546 // If this is the integer domain make sure to check both integer columns.
6547 for (const uint16_t (&Row)[4] : Table)
6548 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6549 return Row;
6550 return nullptr;
6551 }
6552
6553 // Helper to attempt to widen/narrow blend masks.
6554 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6555 unsigned NewWidth, unsigned *pNewMask = nullptr) {
6556 assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6557 "Illegal blend mask scale");
6558 unsigned NewMask = 0;
6559
6560 if ((OldWidth % NewWidth) == 0) {
6561 unsigned Scale = OldWidth / NewWidth;
6562 unsigned SubMask = (1u << Scale) - 1;
6563 for (unsigned i = 0; i != NewWidth; ++i) {
6564 unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6565 if (Sub == SubMask)
6566 NewMask |= (1u << i);
6567 else if (Sub != 0x0)
6568 return false;
6569 }
6570 } else {
6571 unsigned Scale = NewWidth / OldWidth;
6572 unsigned SubMask = (1u << Scale) - 1;
6573 for (unsigned i = 0; i != OldWidth; ++i) {
6574 if (OldMask & (1 << i)) {
6575 NewMask |= (SubMask << (i * Scale));
6576 }
6577 }
6578 }
6579
6580 if (pNewMask)
6581 *pNewMask = NewMask;
6582 return true;
6583 }
6584
6585 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6586 unsigned Opcode = MI.getOpcode();
6587 unsigned NumOperands = MI.getDesc().getNumOperands();
6588
6589 auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6590 uint16_t validDomains = 0;
6591 if (MI.getOperand(NumOperands - 1).isImm()) {
6592 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6593 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6594 validDomains |= 0x2; // PackedSingle
6595 if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6596 validDomains |= 0x4; // PackedDouble
6597 if (!Is256 || Subtarget.hasAVX2())
6598 validDomains |= 0x8; // PackedInt
6599 }
6600 return validDomains;
6601 };
6602
6603 switch (Opcode) {
6604 case X86::BLENDPDrmi:
6605 case X86::BLENDPDrri:
6606 case X86::VBLENDPDrmi:
6607 case X86::VBLENDPDrri:
6608 return GetBlendDomains(2, false);
6609 case X86::VBLENDPDYrmi:
6610 case X86::VBLENDPDYrri:
6611 return GetBlendDomains(4, true);
6612 case X86::BLENDPSrmi:
6613 case X86::BLENDPSrri:
6614 case X86::VBLENDPSrmi:
6615 case X86::VBLENDPSrri:
6616 case X86::VPBLENDDrmi:
6617 case X86::VPBLENDDrri:
6618 return GetBlendDomains(4, false);
6619 case X86::VBLENDPSYrmi:
6620 case X86::VBLENDPSYrri:
6621 case X86::VPBLENDDYrmi:
6622 case X86::VPBLENDDYrri:
6623 return GetBlendDomains(8, true);
6624 case X86::PBLENDWrmi:
6625 case X86::PBLENDWrri:
6626 case X86::VPBLENDWrmi:
6627 case X86::VPBLENDWrri:
6628 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6629 case X86::VPBLENDWYrmi:
6630 case X86::VPBLENDWYrri:
6631 return GetBlendDomains(8, false);
6632 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6633 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6634 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6635 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6636 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6637 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6638 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6639 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6640 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6641 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6642 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6643 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6644 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6645 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6646 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6647 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm:
6648 // If we don't have DQI see if we can still switch from an EVEX integer
6649 // instruction to a VEX floating point instruction.
6650 if (Subtarget.hasDQI())
6651 return 0;
6652
6653 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6654 return 0;
6655 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6656 return 0;
6657 // Register forms will have 3 operands. Memory form will have more.
6658 if (NumOperands == 3 &&
6659 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6660 return 0;
6661
6662 // All domains are valid.
6663 return 0xe;
6664 case X86::MOVHLPSrr:
6665 // We can swap domains when both inputs are the same register.
6666 // FIXME: This doesn't catch all the cases we would like. If the input
6667 // register isn't KILLed by the instruction, the two address instruction
6668 // pass puts a COPY on one input. The other input uses the original
6669 // register. This prevents the same physical register from being used by
6670 // both inputs.
6671 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6672 MI.getOperand(0).getSubReg() == 0 &&
6673 MI.getOperand(1).getSubReg() == 0 &&
6674 MI.getOperand(2).getSubReg() == 0)
6675 return 0x6;
6676 return 0;
6677 case X86::SHUFPDrri:
6678 return 0x6;
6679 }
6680 return 0;
6681 }
6682
6683 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6684 unsigned Domain) const {
6685 assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6686 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6687 assert(dom && "Not an SSE instruction");
6688
6689 unsigned Opcode = MI.getOpcode();
6690 unsigned NumOperands = MI.getDesc().getNumOperands();
6691
6692 auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6693 if (MI.getOperand(NumOperands - 1).isImm()) {
6694 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6695 Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6696 unsigned NewImm = Imm;
6697
6698 const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
6699 if (!table)
6700 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6701
6702 if (Domain == 1) { // PackedSingle
6703 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6704 } else if (Domain == 2) { // PackedDouble
6705 AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6706 } else if (Domain == 3) { // PackedInt
6707 if (Subtarget.hasAVX2()) {
6708 // If we are already VPBLENDW use that, else use VPBLENDD.
6709 if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6710 table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6711 AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6712 }
6713 } else {
6714 assert(!Is256 && "128-bit vector expected");
6715 AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6716 }
6717 }
6718
6719 assert(table && table[Domain - 1] && "Unknown domain op");
6720 MI.setDesc(get(table[Domain - 1]));
6721 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6722 }
6723 return true;
6724 };
6725
6726 switch (Opcode) {
6727 case X86::BLENDPDrmi:
6728 case X86::BLENDPDrri:
6729 case X86::VBLENDPDrmi:
6730 case X86::VBLENDPDrri:
6731 return SetBlendDomain(2, false);
6732 case X86::VBLENDPDYrmi:
6733 case X86::VBLENDPDYrri:
6734 return SetBlendDomain(4, true);
6735 case X86::BLENDPSrmi:
6736 case X86::BLENDPSrri:
6737 case X86::VBLENDPSrmi:
6738 case X86::VBLENDPSrri:
6739 case X86::VPBLENDDrmi:
6740 case X86::VPBLENDDrri:
6741 return SetBlendDomain(4, false);
6742 case X86::VBLENDPSYrmi:
6743 case X86::VBLENDPSYrri:
6744 case X86::VPBLENDDYrmi:
6745 case X86::VPBLENDDYrri:
6746 return SetBlendDomain(8, true);
6747 case X86::PBLENDWrmi:
6748 case X86::PBLENDWrri:
6749 case X86::VPBLENDWrmi:
6750 case X86::VPBLENDWrri:
6751 return SetBlendDomain(8, false);
6752 case X86::VPBLENDWYrmi:
6753 case X86::VPBLENDWYrri:
6754 return SetBlendDomain(16, true);
6755 case X86::VPANDDZ128rr: case X86::VPANDDZ128rm:
6756 case X86::VPANDDZ256rr: case X86::VPANDDZ256rm:
6757 case X86::VPANDQZ128rr: case X86::VPANDQZ128rm:
6758 case X86::VPANDQZ256rr: case X86::VPANDQZ256rm:
6759 case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6760 case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6761 case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6762 case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6763 case X86::VPORDZ128rr: case X86::VPORDZ128rm:
6764 case X86::VPORDZ256rr: case X86::VPORDZ256rm:
6765 case X86::VPORQZ128rr: case X86::VPORQZ128rm:
6766 case X86::VPORQZ256rr: case X86::VPORQZ256rm:
6767 case X86::VPXORDZ128rr: case X86::VPXORDZ128rm:
6768 case X86::VPXORDZ256rr: case X86::VPXORDZ256rm:
6769 case X86::VPXORQZ128rr: case X86::VPXORQZ128rm:
6770 case X86::VPXORQZ256rr: case X86::VPXORQZ256rm: {
6771 // Without DQI, convert EVEX instructions to VEX instructions.
6772 if (Subtarget.hasDQI())
6773 return false;
6774
6775 const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6776 ReplaceableCustomAVX512LogicInstrs);
6777 assert(table && "Instruction not found in table?");
6778 // Don't change integer Q instructions to D instructions and
6779 // use D intructions if we started with a PS instruction.
6780 if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6781 Domain = 4;
6782 MI.setDesc(get(table[Domain - 1]));
6783 return true;
6784 }
6785 case X86::UNPCKHPDrr:
6786 case X86::MOVHLPSrr:
6787 // We just need to commute the instruction which will switch the domains.
6788 if (Domain != dom && Domain != 3 &&
6789 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6790 MI.getOperand(0).getSubReg() == 0 &&
6791 MI.getOperand(1).getSubReg() == 0 &&
6792 MI.getOperand(2).getSubReg() == 0) {
6793 commuteInstruction(MI, false);
6794 return true;
6795 }
6796 // We must always return true for MOVHLPSrr.
6797 if (Opcode == X86::MOVHLPSrr)
6798 return true;
6799 break;
6800 case X86::SHUFPDrri: {
6801 if (Domain == 1) {
6802 unsigned Imm = MI.getOperand(3).getImm();
6803 unsigned NewImm = 0x44;
6804 if (Imm & 1) NewImm |= 0x0a;
6805 if (Imm & 2) NewImm |= 0xa0;
6806 MI.getOperand(3).setImm(NewImm);
6807 MI.setDesc(get(X86::SHUFPSrri));
6808 }
6809 return true;
6810 }
6811 }
6812 return false;
6813 }
6814
6815 std::pair<uint16_t, uint16_t>
6816 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6817 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6818 unsigned opcode = MI.getOpcode();
6819 uint16_t validDomains = 0;
6820 if (domain) {
6821 // Attempt to match for custom instructions.
6822 validDomains = getExecutionDomainCustom(MI);
6823 if (validDomains)
6824 return std::make_pair(domain, validDomains);
6825
6826 if (lookup(opcode, domain, ReplaceableInstrs)) {
6827 validDomains = 0xe;
6828 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6829 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6830 } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
6831 validDomains = 0x6;
6832 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6833 // Insert/extract instructions should only effect domain if AVX2
6834 // is enabled.
6835 if (!Subtarget.hasAVX2())
6836 return std::make_pair(0, 0);
6837 validDomains = 0xe;
6838 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6839 validDomains = 0xe;
6840 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6841 ReplaceableInstrsAVX512DQ)) {
6842 validDomains = 0xe;
6843 } else if (Subtarget.hasDQI()) {
6844 if (const uint16_t *table = lookupAVX512(opcode, domain,
6845 ReplaceableInstrsAVX512DQMasked)) {
6846 if (domain == 1 || (domain == 3 && table[3] == opcode))
6847 validDomains = 0xa;
6848 else
6849 validDomains = 0xc;
6850 }
6851 }
6852 }
6853 return std::make_pair(domain, validDomains);
6854 }
6855
6856 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6857 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6858 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6859 assert(dom && "Not an SSE instruction");
6860
6861 // Attempt to match for custom instructions.
6862 if (setExecutionDomainCustom(MI, Domain))
6863 return;
6864
6865 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6866 if (!table) { // try the other table
6867 assert((Subtarget.hasAVX2() || Domain < 3) &&
6868 "256-bit vector operations only available in AVX2");
6869 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6870 }
6871 if (!table) { // try the FP table
6872 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
6873 assert((!table || Domain < 3) &&
6874 "Can only select PackedSingle or PackedDouble");
6875 }
6876 if (!table) { // try the other table
6877 assert(Subtarget.hasAVX2() &&
6878 "256-bit insert/extract only available in AVX2");
6879 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6880 }
6881 if (!table) { // try the AVX512 table
6882 assert(Subtarget.hasAVX512() && "Requires AVX-512");
6883 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6884 // Don't change integer Q instructions to D instructions.
6885 if (table && Domain == 3 && table[3] == MI.getOpcode())
6886 Domain = 4;
6887 }
6888 if (!table) { // try the AVX512DQ table
6889 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6890 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6891 // Don't change integer Q instructions to D instructions and
6892 // use D intructions if we started with a PS instruction.
6893 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6894 Domain = 4;
6895 }
6896 if (!table) { // try the AVX512DQMasked table
6897 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6898 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6899 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6900 Domain = 4;
6901 }
6902 assert(table && "Cannot change domain");
6903 MI.setDesc(get(table[Domain - 1]));
6904 }
6905
6906 /// Return the noop instruction to use for a noop.
6907 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6908 NopInst.setOpcode(X86::NOOP);
6909 }
6910
6911 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6912 switch (opc) {
6913 default: return false;
6914 case X86::DIVPDrm:
6915 case X86::DIVPDrr:
6916 case X86::DIVPSrm:
6917 case X86::DIVPSrr:
6918 case X86::DIVSDrm:
6919 case X86::DIVSDrm_Int:
6920 case X86::DIVSDrr:
6921 case X86::DIVSDrr_Int:
6922 case X86::DIVSSrm:
6923 case X86::DIVSSrm_Int:
6924 case X86::DIVSSrr:
6925 case X86::DIVSSrr_Int:
6926 case X86::SQRTPDm:
6927 case X86::SQRTPDr:
6928 case X86::SQRTPSm:
6929 case X86::SQRTPSr:
6930 case X86::SQRTSDm:
6931 case X86::SQRTSDm_Int:
6932 case X86::SQRTSDr:
6933 case X86::SQRTSDr_Int:
6934 case X86::SQRTSSm:
6935 case X86::SQRTSSm_Int:
6936 case X86::SQRTSSr:
6937 case X86::SQRTSSr_Int:
6938 // AVX instructions with high latency
6939 case X86::VDIVPDrm:
6940 case X86::VDIVPDrr:
6941 case X86::VDIVPDYrm:
6942 case X86::VDIVPDYrr:
6943 case X86::VDIVPSrm:
6944 case X86::VDIVPSrr:
6945 case X86::VDIVPSYrm:
6946 case X86::VDIVPSYrr:
6947 case X86::VDIVSDrm:
6948 case X86::VDIVSDrm_Int:
6949 case X86::VDIVSDrr:
6950 case X86::VDIVSDrr_Int:
6951 case X86::VDIVSSrm:
6952 case X86::VDIVSSrm_Int:
6953 case X86::VDIVSSrr:
6954 case X86::VDIVSSrr_Int:
6955 case X86::VSQRTPDm:
6956 case X86::VSQRTPDr:
6957 case X86::VSQRTPDYm:
6958 case X86::VSQRTPDYr:
6959 case X86::VSQRTPSm:
6960 case X86::VSQRTPSr:
6961 case X86::VSQRTPSYm:
6962 case X86::VSQRTPSYr:
6963 case X86::VSQRTSDm:
6964 case X86::VSQRTSDm_Int:
6965 case X86::VSQRTSDr:
6966 case X86::VSQRTSDr_Int:
6967 case X86::VSQRTSSm:
6968 case X86::VSQRTSSm_Int:
6969 case X86::VSQRTSSr:
6970 case X86::VSQRTSSr_Int:
6971 // AVX512 instructions with high latency
6972 case X86::VDIVPDZ128rm:
6973 case X86::VDIVPDZ128rmb:
6974 case X86::VDIVPDZ128rmbk:
6975 case X86::VDIVPDZ128rmbkz:
6976 case X86::VDIVPDZ128rmk:
6977 case X86::VDIVPDZ128rmkz:
6978 case X86::VDIVPDZ128rr:
6979 case X86::VDIVPDZ128rrk:
6980 case X86::VDIVPDZ128rrkz:
6981 case X86::VDIVPDZ256rm:
6982 case X86::VDIVPDZ256rmb:
6983 case X86::VDIVPDZ256rmbk:
6984 case X86::VDIVPDZ256rmbkz:
6985 case X86::VDIVPDZ256rmk:
6986 case X86::VDIVPDZ256rmkz:
6987 case X86::VDIVPDZ256rr:
6988 case X86::VDIVPDZ256rrk:
6989 case X86::VDIVPDZ256rrkz:
6990 case X86::VDIVPDZrrb:
6991 case X86::VDIVPDZrrbk:
6992 case X86::VDIVPDZrrbkz:
6993 case X86::VDIVPDZrm:
6994 case X86::VDIVPDZrmb:
6995 case X86::VDIVPDZrmbk:
6996 case X86::VDIVPDZrmbkz:
6997 case X86::VDIVPDZrmk:
6998 case X86::VDIVPDZrmkz:
6999 case X86::VDIVPDZrr:
7000 case X86::VDIVPDZrrk:
7001 case X86::VDIVPDZrrkz:
7002 case X86::VDIVPSZ128rm:
7003 case X86::VDIVPSZ128rmb:
7004 case X86::VDIVPSZ128rmbk:
7005 case X86::VDIVPSZ128rmbkz:
7006 case X86::VDIVPSZ128rmk:
7007 case X86::VDIVPSZ128rmkz:
7008 case X86::VDIVPSZ128rr:
7009 case X86::VDIVPSZ128rrk:
7010 case X86::VDIVPSZ128rrkz:
7011 case X86::VDIVPSZ256rm:
7012 case X86::VDIVPSZ256rmb:
7013 case X86::VDIVPSZ256rmbk:
7014 case X86::VDIVPSZ256rmbkz:
7015 case X86::VDIVPSZ256rmk:
7016 case X86::VDIVPSZ256rmkz:
7017 case X86::VDIVPSZ256rr:
7018 case X86::VDIVPSZ256rrk:
7019 case X86::VDIVPSZ256rrkz:
7020 case X86::VDIVPSZrrb:
7021 case X86::VDIVPSZrrbk:
7022 case X86::VDIVPSZrrbkz:
7023 case X86::VDIVPSZrm:
7024 case X86::VDIVPSZrmb:
7025 case X86::VDIVPSZrmbk:
7026 case X86::VDIVPSZrmbkz:
7027 case X86::VDIVPSZrmk:
7028 case X86::VDIVPSZrmkz:
7029 case X86::VDIVPSZrr:
7030 case X86::VDIVPSZrrk:
7031 case X86::VDIVPSZrrkz:
7032 case X86::VDIVSDZrm:
7033 case X86::VDIVSDZrr:
7034 case X86::VDIVSDZrm_Int:
7035 case X86::VDIVSDZrm_Intk:
7036 case X86::VDIVSDZrm_Intkz:
7037 case X86::VDIVSDZrr_Int:
7038 case X86::VDIVSDZrr_Intk:
7039 case X86::VDIVSDZrr_Intkz:
7040 case X86::VDIVSDZrrb_Int:
7041 case X86::VDIVSDZrrb_Intk:
7042 case X86::VDIVSDZrrb_Intkz:
7043 case X86::VDIVSSZrm:
7044 case X86::VDIVSSZrr:
7045 case X86::VDIVSSZrm_Int:
7046 case X86::VDIVSSZrm_Intk:
7047 case X86::VDIVSSZrm_Intkz:
7048 case X86::VDIVSSZrr_Int:
7049 case X86::VDIVSSZrr_Intk:
7050 case X86::VDIVSSZrr_Intkz:
7051 case X86::VDIVSSZrrb_Int:
7052 case X86::VDIVSSZrrb_Intk:
7053 case X86::VDIVSSZrrb_Intkz:
7054 case X86::VSQRTPDZ128m:
7055 case X86::VSQRTPDZ128mb:
7056 case X86::VSQRTPDZ128mbk:
7057 case X86::VSQRTPDZ128mbkz:
7058 case X86::VSQRTPDZ128mk:
7059 case X86::VSQRTPDZ128mkz:
7060 case X86::VSQRTPDZ128r:
7061 case X86::VSQRTPDZ128rk:
7062 case X86::VSQRTPDZ128rkz:
7063 case X86::VSQRTPDZ256m:
7064 case X86::VSQRTPDZ256mb:
7065 case X86::VSQRTPDZ256mbk:
7066 case X86::VSQRTPDZ256mbkz:
7067 case X86::VSQRTPDZ256mk:
7068 case X86::VSQRTPDZ256mkz:
7069 case X86::VSQRTPDZ256r:
7070 case X86::VSQRTPDZ256rk:
7071 case X86::VSQRTPDZ256rkz:
7072 case X86::VSQRTPDZm:
7073 case X86::VSQRTPDZmb:
7074 case X86::VSQRTPDZmbk:
7075 case X86::VSQRTPDZmbkz:
7076 case X86::VSQRTPDZmk:
7077 case X86::VSQRTPDZmkz:
7078 case X86::VSQRTPDZr:
7079 case X86::VSQRTPDZrb:
7080 case X86::VSQRTPDZrbk:
7081 case X86::VSQRTPDZrbkz:
7082 case X86::VSQRTPDZrk:
7083 case X86::VSQRTPDZrkz:
7084 case X86::VSQRTPSZ128m:
7085 case X86::VSQRTPSZ128mb:
7086 case X86::VSQRTPSZ128mbk:
7087 case X86::VSQRTPSZ128mbkz:
7088 case X86::VSQRTPSZ128mk:
7089 case X86::VSQRTPSZ128mkz:
7090 case X86::VSQRTPSZ128r:
7091 case X86::VSQRTPSZ128rk:
7092 case X86::VSQRTPSZ128rkz:
7093 case X86::VSQRTPSZ256m:
7094 case X86::VSQRTPSZ256mb:
7095 case X86::VSQRTPSZ256mbk:
7096 case X86::VSQRTPSZ256mbkz:
7097 case X86::VSQRTPSZ256mk:
7098 case X86::VSQRTPSZ256mkz:
7099 case X86::VSQRTPSZ256r:
7100 case X86::VSQRTPSZ256rk:
7101 case X86::VSQRTPSZ256rkz:
7102 case X86::VSQRTPSZm:
7103 case X86::VSQRTPSZmb:
7104 case X86::VSQRTPSZmbk:
7105 case X86::VSQRTPSZmbkz:
7106 case X86::VSQRTPSZmk:
7107 case X86::VSQRTPSZmkz:
7108 case X86::VSQRTPSZr:
7109 case X86::VSQRTPSZrb:
7110 case X86::VSQRTPSZrbk:
7111 case X86::VSQRTPSZrbkz:
7112 case X86::VSQRTPSZrk:
7113 case X86::VSQRTPSZrkz:
7114 case X86::VSQRTSDZm:
7115 case X86::VSQRTSDZm_Int:
7116 case X86::VSQRTSDZm_Intk:
7117 case X86::VSQRTSDZm_Intkz:
7118 case X86::VSQRTSDZr:
7119 case X86::VSQRTSDZr_Int:
7120 case X86::VSQRTSDZr_Intk:
7121 case X86::VSQRTSDZr_Intkz:
7122 case X86::VSQRTSDZrb_Int:
7123 case X86::VSQRTSDZrb_Intk:
7124 case X86::VSQRTSDZrb_Intkz:
7125 case X86::VSQRTSSZm:
7126 case X86::VSQRTSSZm_Int:
7127 case X86::VSQRTSSZm_Intk:
7128 case X86::VSQRTSSZm_Intkz:
7129 case X86::VSQRTSSZr:
7130 case X86::VSQRTSSZr_Int:
7131 case X86::VSQRTSSZr_Intk:
7132 case X86::VSQRTSSZr_Intkz:
7133 case X86::VSQRTSSZrb_Int:
7134 case X86::VSQRTSSZrb_Intk:
7135 case X86::VSQRTSSZrb_Intkz:
7136
7137 case X86::VGATHERDPDYrm:
7138 case X86::VGATHERDPDZ128rm:
7139 case X86::VGATHERDPDZ256rm:
7140 case X86::VGATHERDPDZrm:
7141 case X86::VGATHERDPDrm:
7142 case X86::VGATHERDPSYrm:
7143 case X86::VGATHERDPSZ128rm:
7144 case X86::VGATHERDPSZ256rm:
7145 case X86::VGATHERDPSZrm:
7146 case X86::VGATHERDPSrm:
7147 case X86::VGATHERPF0DPDm:
7148 case X86::VGATHERPF0DPSm:
7149 case X86::VGATHERPF0QPDm:
7150 case X86::VGATHERPF0QPSm:
7151 case X86::VGATHERPF1DPDm:
7152 case X86::VGATHERPF1DPSm:
7153 case X86::VGATHERPF1QPDm:
7154 case X86::VGATHERPF1QPSm:
7155 case X86::VGATHERQPDYrm:
7156 case X86::VGATHERQPDZ128rm:
7157 case X86::VGATHERQPDZ256rm:
7158 case X86::VGATHERQPDZrm:
7159 case X86::VGATHERQPDrm:
7160 case X86::VGATHERQPSYrm:
7161 case X86::VGATHERQPSZ128rm:
7162 case X86::VGATHERQPSZ256rm:
7163 case X86::VGATHERQPSZrm:
7164 case X86::VGATHERQPSrm:
7165 case X86::VPGATHERDDYrm:
7166 case X86::VPGATHERDDZ128rm:
7167 case X86::VPGATHERDDZ256rm:
7168 case X86::VPGATHERDDZrm:
7169 case X86::VPGATHERDDrm:
7170 case X86::VPGATHERDQYrm:
7171 case X86::VPGATHERDQZ128rm:
7172 case X86::VPGATHERDQZ256rm:
7173 case X86::VPGATHERDQZrm:
7174 case X86::VPGATHERDQrm:
7175 case X86::VPGATHERQDYrm:
7176 case X86::VPGATHERQDZ128rm:
7177 case X86::VPGATHERQDZ256rm:
7178 case X86::VPGATHERQDZrm:
7179 case X86::VPGATHERQDrm:
7180 case X86::VPGATHERQQYrm:
7181 case X86::VPGATHERQQZ128rm:
7182 case X86::VPGATHERQQZ256rm:
7183 case X86::VPGATHERQQZrm:
7184 case X86::VPGATHERQQrm:
7185 case X86::VSCATTERDPDZ128mr:
7186 case X86::VSCATTERDPDZ256mr:
7187 case X86::VSCATTERDPDZmr:
7188 case X86::VSCATTERDPSZ128mr:
7189 case X86::VSCATTERDPSZ256mr:
7190 case X86::VSCATTERDPSZmr:
7191 case X86::VSCATTERPF0DPDm:
7192 case X86::VSCATTERPF0DPSm:
7193 case X86::VSCATTERPF0QPDm:
7194 case X86::VSCATTERPF0QPSm:
7195 case X86::VSCATTERPF1DPDm:
7196 case X86::VSCATTERPF1DPSm:
7197 case X86::VSCATTERPF1QPDm:
7198 case X86::VSCATTERPF1QPSm:
7199 case X86::VSCATTERQPDZ128mr:
7200 case X86::VSCATTERQPDZ256mr:
7201 case X86::VSCATTERQPDZmr:
7202 case X86::VSCATTERQPSZ128mr:
7203 case X86::VSCATTERQPSZ256mr:
7204 case X86::VSCATTERQPSZmr:
7205 case X86::VPSCATTERDDZ128mr:
7206 case X86::VPSCATTERDDZ256mr:
7207 case X86::VPSCATTERDDZmr:
7208 case X86::VPSCATTERDQZ128mr:
7209 case X86::VPSCATTERDQZ256mr:
7210 case X86::VPSCATTERDQZmr:
7211 case X86::VPSCATTERQDZ128mr:
7212 case X86::VPSCATTERQDZ256mr:
7213 case X86::VPSCATTERQDZmr:
7214 case X86::VPSCATTERQQZ128mr:
7215 case X86::VPSCATTERQQZ256mr:
7216 case X86::VPSCATTERQQZmr:
7217 return true;
7218 }
7219 }
7220
7221 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7222 const MachineRegisterInfo *MRI,
7223 const MachineInstr &DefMI,
7224 unsigned DefIdx,
7225 const MachineInstr &UseMI,
7226 unsigned UseIdx) const {
7227 return isHighLatencyDef(DefMI.getOpcode());
7228 }
7229
7230 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7231 const MachineBasicBlock *MBB) const {
7232 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7233 "Reassociation needs binary operators");
7234
7235 // Integer binary math/logic instructions have a third source operand:
7236 // the EFLAGS register. That operand must be both defined here and never
7237 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7238 // not change anything because rearranging the operands could affect other
7239 // instructions that depend on the exact status flags (zero, sign, etc.)
7240 // that are set by using these particular operands with this operation.
7241 if (Inst.getNumOperands() == 4) {
7242 assert(Inst.getOperand(3).isReg() &&
7243 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7244 "Unexpected operand in reassociable instruction");
7245 if (!Inst.getOperand(3).isDead())
7246 return false;
7247 }
7248
7249 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7250 }
7251
7252 // TODO: There are many more machine instruction opcodes to match:
7253 // 1. Other data types (integer, vectors)
7254 // 2. Other math / logic operations (xor, or)
7255 // 3. Other forms of the same operation (intrinsics and other variants)
7256 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7257 switch (Inst.getOpcode()) {
7258 case X86::AND8rr:
7259 case X86::AND16rr:
7260 case X86::AND32rr:
7261 case X86::AND64rr:
7262 case X86::OR8rr:
7263 case X86::OR16rr:
7264 case X86::OR32rr:
7265 case X86::OR64rr:
7266 case X86::XOR8rr:
7267 case X86::XOR16rr:
7268 case X86::XOR32rr:
7269 case X86::XOR64rr:
7270 case X86::IMUL16rr:
7271 case X86::IMUL32rr:
7272 case X86::IMUL64rr:
7273 case X86::PANDrr:
7274 case X86::PORrr:
7275 case X86::PXORrr:
7276 case X86::ANDPDrr:
7277 case X86::ANDPSrr:
7278 case X86::ORPDrr:
7279 case X86::ORPSrr:
7280 case X86::XORPDrr:
7281 case X86::XORPSrr:
7282 case X86::PADDBrr:
7283 case X86::PADDWrr:
7284 case X86::PADDDrr:
7285 case X86::PADDQrr:
7286 case X86::PMULLWrr:
7287 case X86::PMULLDrr:
7288 case X86::PMAXSBrr:
7289 case X86::PMAXSDrr:
7290 case X86::PMAXSWrr:
7291 case X86::PMAXUBrr:
7292 case X86::PMAXUDrr:
7293 case X86::PMAXUWrr:
7294 case X86::PMINSBrr:
7295 case X86::PMINSDrr:
7296 case X86::PMINSWrr:
7297 case X86::PMINUBrr:
7298 case X86::PMINUDrr:
7299 case X86::PMINUWrr:
7300 case X86::VPANDrr:
7301 case X86::VPANDYrr:
7302 case X86::VPANDDZ128rr:
7303 case X86::VPANDDZ256rr:
7304 case X86::VPANDDZrr:
7305 case X86::VPANDQZ128rr:
7306 case X86::VPANDQZ256rr:
7307 case X86::VPANDQZrr:
7308 case X86::VPORrr:
7309 case X86::VPORYrr:
7310 case X86::VPORDZ128rr:
7311 case X86::VPORDZ256rr:
7312 case X86::VPORDZrr:
7313 case X86::VPORQZ128rr:
7314 case X86::VPORQZ256rr:
7315 case X86::VPORQZrr:
7316 case X86::VPXORrr:
7317 case X86::VPXORYrr:
7318 case X86::VPXORDZ128rr:
7319 case X86::VPXORDZ256rr:
7320 case X86::VPXORDZrr:
7321 case X86::VPXORQZ128rr:
7322 case X86::VPXORQZ256rr:
7323 case X86::VPXORQZrr:
7324 case X86::VANDPDrr:
7325 case X86::VANDPSrr:
7326 case X86::VANDPDYrr:
7327 case X86::VANDPSYrr:
7328 case X86::VANDPDZ128rr:
7329 case X86::VANDPSZ128rr:
7330 case X86::VANDPDZ256rr:
7331 case X86::VANDPSZ256rr:
7332 case X86::VANDPDZrr:
7333 case X86::VANDPSZrr:
7334 case X86::VORPDrr:
7335 case X86::VORPSrr:
7336 case X86::VORPDYrr:
7337 case X86::VORPSYrr:
7338 case X86::VORPDZ128rr:
7339 case X86::VORPSZ128rr:
7340 case X86::VORPDZ256rr:
7341 case X86::VORPSZ256rr:
7342 case X86::VORPDZrr:
7343 case X86::VORPSZrr:
7344 case X86::VXORPDrr:
7345 case X86::VXORPSrr:
7346 case X86::VXORPDYrr:
7347 case X86::VXORPSYrr:
7348 case X86::VXORPDZ128rr:
7349 case X86::VXORPSZ128rr:
7350 case X86::VXORPDZ256rr:
7351 case X86::VXORPSZ256rr:
7352 case X86::VXORPDZrr:
7353 case X86::VXORPSZrr:
7354 case X86::KADDBrr:
7355 case X86::KADDWrr:
7356 case X86::KADDDrr:
7357 case X86::KADDQrr:
7358 case X86::KANDBrr:
7359 case X86::KANDWrr:
7360 case X86::KANDDrr:
7361 case X86::KANDQrr:
7362 case X86::KORBrr:
7363 case X86::KORWrr:
7364 case X86::KORDrr:
7365 case X86::KORQrr:
7366 case X86::KXORBrr:
7367 case X86::KXORWrr:
7368 case X86::KXORDrr:
7369 case X86::KXORQrr:
7370 case X86::VPADDBrr:
7371 case X86::VPADDWrr:
7372 case X86::VPADDDrr:
7373 case X86::VPADDQrr:
7374 case X86::VPADDBYrr:
7375 case X86::VPADDWYrr:
7376 case X86::VPADDDYrr:
7377 case X86::VPADDQYrr:
7378 case X86::VPADDBZ128rr:
7379 case X86::VPADDWZ128rr:
7380 case X86::VPADDDZ128rr:
7381 case X86::VPADDQZ128rr:
7382 case X86::VPADDBZ256rr:
7383 case X86::VPADDWZ256rr:
7384 case X86::VPADDDZ256rr:
7385 case X86::VPADDQZ256rr:
7386 case X86::VPADDBZrr:
7387 case X86::VPADDWZrr:
7388 case X86::VPADDDZrr:
7389 case X86::VPADDQZrr:
7390 case X86::VPMULLWrr:
7391 case X86::VPMULLWYrr:
7392 case X86::VPMULLWZ128rr:
7393 case X86::VPMULLWZ256rr:
7394 case X86::VPMULLWZrr:
7395 case X86::VPMULLDrr:
7396 case X86::VPMULLDYrr:
7397 case X86::VPMULLDZ128rr:
7398 case X86::VPMULLDZ256rr:
7399 case X86::VPMULLDZrr:
7400 case X86::VPMULLQZ128rr:
7401 case X86::VPMULLQZ256rr:
7402 case X86::VPMULLQZrr:
7403 case X86::VPMAXSBrr:
7404 case X86::VPMAXSBYrr:
7405 case X86::VPMAXSBZ128rr:
7406 case X86::VPMAXSBZ256rr:
7407 case X86::VPMAXSBZrr:
7408 case X86::VPMAXSDrr:
7409 case X86::VPMAXSDYrr:
7410 case X86::VPMAXSDZ128rr:
7411 case X86::VPMAXSDZ256rr:
7412 case X86::VPMAXSDZrr:
7413 case X86::VPMAXSQZ128rr:
7414 case X86::VPMAXSQZ256rr:
7415 case X86::VPMAXSQZrr:
7416 case X86::VPMAXSWrr:
7417 case X86::VPMAXSWYrr:
7418 case X86::VPMAXSWZ128rr:
7419 case X86::VPMAXSWZ256rr:
7420 case X86::VPMAXSWZrr:
7421 case X86::VPMAXUBrr:
7422 case X86::VPMAXUBYrr:
7423 case X86::VPMAXUBZ128rr:
7424 case X86::VPMAXUBZ256rr:
7425 case X86::VPMAXUBZrr:
7426 case X86::VPMAXUDrr:
7427 case X86::VPMAXUDYrr:
7428 case X86::VPMAXUDZ128rr:
7429 case X86::VPMAXUDZ256rr:
7430 case X86::VPMAXUDZrr:
7431 case X86::VPMAXUQZ128rr:
7432 case X86::VPMAXUQZ256rr:
7433 case X86::VPMAXUQZrr:
7434 case X86::VPMAXUWrr:
7435 case X86::VPMAXUWYrr:
7436 case X86::VPMAXUWZ128rr:
7437 case X86::VPMAXUWZ256rr:
7438 case X86::VPMAXUWZrr:
7439 case X86::VPMINSBrr:
7440 case X86::VPMINSBYrr:
7441 case X86::VPMINSBZ128rr:
7442 case X86::VPMINSBZ256rr:
7443 case X86::VPMINSBZrr:
7444 case X86::VPMINSDrr:
7445 case X86::VPMINSDYrr:
7446 case X86::VPMINSDZ128rr:
7447 case X86::VPMINSDZ256rr:
7448 case X86::VPMINSDZrr:
7449 case X86::VPMINSQZ128rr:
7450 case X86::VPMINSQZ256rr:
7451 case X86::VPMINSQZrr:
7452 case X86::VPMINSWrr:
7453 case X86::VPMINSWYrr:
7454 case X86::VPMINSWZ128rr:
7455 case X86::VPMINSWZ256rr:
7456 case X86::VPMINSWZrr:
7457 case X86::VPMINUBrr:
7458 case X86::VPMINUBYrr:
7459 case X86::VPMINUBZ128rr:
7460 case X86::VPMINUBZ256rr:
7461 case X86::VPMINUBZrr:
7462 case X86::VPMINUDrr:
7463 case X86::VPMINUDYrr:
7464 case X86::VPMINUDZ128rr:
7465 case X86::VPMINUDZ256rr:
7466 case X86::VPMINUDZrr:
7467 case X86::VPMINUQZ128rr:
7468 case X86::VPMINUQZ256rr:
7469 case X86::VPMINUQZrr:
7470 case X86::VPMINUWrr:
7471 case X86::VPMINUWYrr:
7472 case X86::VPMINUWZ128rr:
7473 case X86::VPMINUWZ256rr:
7474 case X86::VPMINUWZrr:
7475 // Normal min/max instructions are not commutative because of NaN and signed
7476 // zero semantics, but these are. Thus, there's no need to check for global
7477 // relaxed math; the instructions themselves have the properties we need.
7478 case X86::MAXCPDrr:
7479 case X86::MAXCPSrr:
7480 case X86::MAXCSDrr:
7481 case X86::MAXCSSrr:
7482 case X86::MINCPDrr:
7483 case X86::MINCPSrr:
7484 case X86::MINCSDrr:
7485 case X86::MINCSSrr:
7486 case X86::VMAXCPDrr:
7487 case X86::VMAXCPSrr:
7488 case X86::VMAXCPDYrr:
7489 case X86::VMAXCPSYrr:
7490 case X86::VMAXCPDZ128rr:
7491 case X86::VMAXCPSZ128rr:
7492 case X86::VMAXCPDZ256rr:
7493 case X86::VMAXCPSZ256rr:
7494 case X86::VMAXCPDZrr:
7495 case X86::VMAXCPSZrr:
7496 case X86::VMAXCSDrr:
7497 case X86::VMAXCSSrr:
7498 case X86::VMAXCSDZrr:
7499 case X86::VMAXCSSZrr:
7500 case X86::VMINCPDrr:
7501 case X86::VMINCPSrr:
7502 case X86::VMINCPDYrr:
7503 case X86::VMINCPSYrr:
7504 case X86::VMINCPDZ128rr:
7505 case X86::VMINCPSZ128rr:
7506 case X86::VMINCPDZ256rr:
7507 case X86::VMINCPSZ256rr:
7508 case X86::VMINCPDZrr:
7509 case X86::VMINCPSZrr:
7510 case X86::VMINCSDrr:
7511 case X86::VMINCSSrr:
7512 case X86::VMINCSDZrr:
7513 case X86::VMINCSSZrr:
7514 return true;
7515 case X86::ADDPDrr:
7516 case X86::ADDPSrr:
7517 case X86::ADDSDrr:
7518 case X86::ADDSSrr:
7519 case X86::MULPDrr:
7520 case X86::MULPSrr:
7521 case X86::MULSDrr:
7522 case X86::MULSSrr:
7523 case X86::VADDPDrr:
7524 case X86::VADDPSrr:
7525 case X86::VADDPDYrr:
7526 case X86::VADDPSYrr:
7527 case X86::VADDPDZ128rr:
7528 case X86::VADDPSZ128rr:
7529 case X86::VADDPDZ256rr:
7530 case X86::VADDPSZ256rr:
7531 case X86::VADDPDZrr:
7532 case X86::VADDPSZrr:
7533 case X86::VADDSDrr:
7534 case X86::VADDSSrr:
7535 case X86::VADDSDZrr:
7536 case X86::VADDSSZrr:
7537 case X86::VMULPDrr:
7538 case X86::VMULPSrr:
7539 case X86::VMULPDYrr:
7540 case X86::VMULPSYrr:
7541 case X86::VMULPDZ128rr:
7542 case X86::VMULPSZ128rr:
7543 case X86::VMULPDZ256rr:
7544 case X86::VMULPSZ256rr:
7545 case X86::VMULPDZrr:
7546 case X86::VMULPSZrr:
7547 case X86::VMULSDrr:
7548 case X86::VMULSSrr:
7549 case X86::VMULSDZrr:
7550 case X86::VMULSSZrr:
7551 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7552 default:
7553 return false;
7554 }
7555 }
7556
7557 Optional<ParamLoadedValue>
7558 X86InstrInfo::describeLoadedValue(const MachineInstr &MI) const {
7559 const MachineOperand *Op = nullptr;
7560 DIExpression *Expr = nullptr;
7561
7562 switch (MI.getOpcode()) {
7563 case X86::LEA32r:
7564 case X86::LEA64r:
7565 case X86::LEA64_32r: {
7566 // Operand 4 could be global address. For now we do not support
7567 // such situation.
7568 if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
7569 return None;
7570
7571 const MachineOperand &Op1 = MI.getOperand(1);
7572 const MachineOperand &Op2 = MI.getOperand(3);
7573 const TargetRegisterInfo *TRI = &getRegisterInfo();
7574 assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7575 Register::isPhysicalRegister(Op2.getReg())));
7576
7577 // Omit situations like:
7578 // %rsi = lea %rsi, 4, ...
7579 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7580 Op2.getReg() == MI.getOperand(0).getReg())
7581 return None;
7582 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7583 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7584 (Op2.getReg() != X86::NoRegister &&
7585 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7586 return None;
7587
7588 int64_t Coef = MI.getOperand(2).getImm();
7589 int64_t Offset = MI.getOperand(4).getImm();
7590 SmallVector<uint64_t, 8> Ops;
7591
7592 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7593 Op = &Op1;
7594 } else if (Op1.isFI())
7595 Op = &Op1;
7596
7597 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7598 Ops.push_back(dwarf::DW_OP_constu);
7599 Ops.push_back(Coef + 1);
7600 Ops.push_back(dwarf::DW_OP_mul);
7601 } else {
7602 if (Op && Op2.getReg() != X86::NoRegister) {
7603 int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
7604 if (dwarfReg < 0)
7605 return None;
7606 else if (dwarfReg < 32) {
7607 Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
7608 Ops.push_back(0);
7609 } else {
7610 Ops.push_back(dwarf::DW_OP_bregx);
7611 Ops.push_back(dwarfReg);
7612 Ops.push_back(0);
7613 }
7614 } else if (!Op) {
7615 assert(Op2.getReg() != X86::NoRegister);
7616 Op = &Op2;
7617 }
7618
7619 if (Coef > 1) {
7620 assert(Op2.getReg() != X86::NoRegister);
7621 Ops.push_back(dwarf::DW_OP_constu);
7622 Ops.push_back(Coef);
7623 Ops.push_back(dwarf::DW_OP_mul);
7624 }
7625
7626 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7627 Op2.getReg() != X86::NoRegister) {
7628 Ops.push_back(dwarf::DW_OP_plus);
7629 }
7630 }
7631
7632 DIExpression::appendOffset(Ops, Offset);
7633 Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
7634
7635 return ParamLoadedValue(*Op, Expr);;
7636 }
7637 case X86::XOR32rr: {
7638 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
7639 return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
7640 return None;
7641 }
7642 default:
7643 return TargetInstrInfo::describeLoadedValue(MI);
7644 }
7645 }
7646
7647 /// This is an architecture-specific helper function of reassociateOps.
7648 /// Set special operand attributes for new instructions after reassociation.
7649 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7650 MachineInstr &OldMI2,
7651 MachineInstr &NewMI1,
7652 MachineInstr &NewMI2) const {
7653 // Integer instructions define an implicit EFLAGS source register operand as
7654 // the third source (fourth total) operand.
7655 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7656 return;
7657
7658 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7659 "Unexpected instruction type for reassociation");
7660
7661 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7662 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7663 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7664 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7665
7666 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7667 "Must have dead EFLAGS operand in reassociable instruction");
7668 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7669 "Must have dead EFLAGS operand in reassociable instruction");
7670
7671 (void)OldOp1;
7672 (void)OldOp2;
7673
7674 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7675 "Unexpected operand in reassociable instruction");
7676 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7677 "Unexpected operand in reassociable instruction");
7678
7679 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7680 // of this pass or other passes. The EFLAGS operands must be dead in these new
7681 // instructions because the EFLAGS operands in the original instructions must
7682 // be dead in order for reassociation to occur.
7683 NewOp1.setIsDead();
7684 NewOp2.setIsDead();
7685 }
7686
7687 std::pair<unsigned, unsigned>
7688 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7689 return std::make_pair(TF, 0u);
7690 }
7691
7692 ArrayRef<std::pair<unsigned, const char *>>
7693 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7694 using namespace X86II;
7695 static const std::pair<unsigned, const char *> TargetFlags[] = {
7696 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7697 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7698 {MO_GOT, "x86-got"},
7699 {MO_GOTOFF, "x86-gotoff"},
7700 {MO_GOTPCREL, "x86-gotpcrel"},
7701 {MO_PLT, "x86-plt"},
7702 {MO_TLSGD, "x86-tlsgd"},
7703 {MO_TLSLD, "x86-tlsld"},
7704 {MO_TLSLDM, "x86-tlsldm"},
7705 {MO_GOTTPOFF, "x86-gottpoff"},
7706 {MO_INDNTPOFF, "x86-indntpoff"},
7707 {MO_TPOFF, "x86-tpoff"},
7708 {MO_DTPOFF, "x86-dtpoff"},
7709 {MO_NTPOFF, "x86-ntpoff"},
7710 {MO_GOTNTPOFF, "x86-gotntpoff"},
7711 {MO_DLLIMPORT, "x86-dllimport"},
7712 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7713 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7714 {MO_TLVP, "x86-tlvp"},
7715 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7716 {MO_SECREL, "x86-secrel"},
7717 {MO_COFFSTUB, "x86-coffstub"}};
7718 return makeArrayRef(TargetFlags);
7719 }
7720
7721 namespace {
7722 /// Create Global Base Reg pass. This initializes the PIC
7723 /// global base register for x86-32.
7724 struct CGBR : public MachineFunctionPass {
7725 static char ID;
7726 CGBR() : MachineFunctionPass(ID) {}
7727
7728 bool runOnMachineFunction(MachineFunction &MF) override {
7729 const X86TargetMachine *TM =
7730 static_cast<const X86TargetMachine *>(&MF.getTarget());
7731 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7732
7733 // Don't do anything in the 64-bit small and kernel code models. They use
7734 // RIP-relative addressing for everything.
7735 if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7736 TM->getCodeModel() == CodeModel::Kernel))
7737 return false;
7738
7739 // Only emit a global base reg in PIC mode.
7740 if (!TM->isPositionIndependent())
7741 return false;
7742
7743 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7744 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7745
7746 // If we didn't need a GlobalBaseReg, don't insert code.
7747 if (GlobalBaseReg == 0)
7748 return false;
7749
7750 // Insert the set of GlobalBaseReg into the first MBB of the function
7751 MachineBasicBlock &FirstMBB = MF.front();
7752 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7753 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7754 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7755 const X86InstrInfo *TII = STI.getInstrInfo();
7756
7757 unsigned PC;
7758 if (STI.isPICStyleGOT())
7759 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7760 else
7761 PC = GlobalBaseReg;
7762
7763 if (STI.is64Bit()) {
7764 if (TM->getCodeModel() == CodeModel::Medium) {
7765 // In the medium code model, use a RIP-relative LEA to materialize the
7766 // GOT.
7767 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7768 .addReg(X86::RIP)
7769 .addImm(0)
7770 .addReg(0)
7771 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7772 .addReg(0);
7773 } else if (TM->getCodeModel() == CodeModel::Large) {
7774 // In the large code model, we are aiming for this code, though the
7775 // register allocation may vary:
7776 // leaq .LN$pb(%rip), %rax
7777 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7778 // addq %rcx, %rax
7779 // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7780 Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7781 Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7782 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7783 .addReg(X86::RIP)
7784 .addImm(0)
7785 .addReg(0)
7786 .addSym(MF.getPICBaseSymbol())
7787 .addReg(0);
7788 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7789 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7790 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7791 X86II::MO_PIC_BASE_OFFSET);
7792 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7793 .addReg(PBReg, RegState::Kill)
7794 .addReg(GOTReg, RegState::Kill);
7795 } else {
7796 llvm_unreachable("unexpected code model");
7797 }
7798 } else {
7799 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7800 // only used in JIT code emission as displacement to pc.
7801 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7802
7803 // If we're using vanilla 'GOT' PIC style, we should use relative
7804 // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7805 if (STI.isPICStyleGOT()) {
7806 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7807 // %some_register
7808 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7809 .addReg(PC)
7810 .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7811 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7812 }
7813 }
7814
7815 return true;
7816 }
7817
7818 StringRef getPassName() const override {
7819 return "X86 PIC Global Base Reg Initialization";
7820 }
7821
7822 void getAnalysisUsage(AnalysisUsage &AU) const override {
7823 AU.setPreservesCFG();
7824 MachineFunctionPass::getAnalysisUsage(AU);
7825 }
7826 };
7827 }
7828
7829 char CGBR::ID = 0;
7830 FunctionPass*
7831 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7832
7833 namespace {
7834 struct LDTLSCleanup : public MachineFunctionPass {
7835 static char ID;
7836 LDTLSCleanup() : MachineFunctionPass(ID) {}
7837
7838 bool runOnMachineFunction(MachineFunction &MF) override {
7839 if (skipFunction(MF.getFunction()))
7840 return false;
7841
7842 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7843 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7844 // No point folding accesses if there isn't at least two.
7845 return false;
7846 }
7847
7848 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7849 return VisitNode(DT->getRootNode(), 0);
7850 }
7851
7852 // Visit the dominator subtree rooted at Node in pre-order.
7853 // If TLSBaseAddrReg is non-null, then use that to replace any
7854 // TLS_base_addr instructions. Otherwise, create the register
7855 // when the first such instruction is seen, and then use it
7856 // as we encounter more instructions.
7857 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7858 MachineBasicBlock *BB = Node->getBlock();
7859 bool Changed = false;
7860
7861 // Traverse the current block.
7862 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7863 ++I) {
7864 switch (I->getOpcode()) {
7865 case X86::TLS_base_addr32:
7866 case X86::TLS_base_addr64:
7867 if (TLSBaseAddrReg)
7868 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7869 else
7870 I = SetRegister(*I, &TLSBaseAddrReg);
7871 Changed = true;
7872 break;
7873 default:
7874 break;
7875 }
7876 }
7877
7878 // Visit the children of this block in the dominator tree.
7879 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7880 I != E; ++I) {
7881 Changed |= VisitNode(*I, TLSBaseAddrReg);
7882 }
7883
7884 return Changed;
7885 }
7886
7887 // Replace the TLS_base_addr instruction I with a copy from
7888 // TLSBaseAddrReg, returning the new instruction.
7889 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7890 unsigned TLSBaseAddrReg) {
7891 MachineFunction *MF = I.getParent()->getParent();
7892 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7893 const bool is64Bit = STI.is64Bit();
7894 const X86InstrInfo *TII = STI.getInstrInfo();
7895
7896 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7897 MachineInstr *Copy =
7898 BuildMI(*I.getParent(), I, I.getDebugLoc(),
7899 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7900 .addReg(TLSBaseAddrReg);
7901
7902 // Erase the TLS_base_addr instruction.
7903 I.eraseFromParent();
7904
7905 return Copy;
7906 }
7907
7908 // Create a virtual register in *TLSBaseAddrReg, and populate it by
7909 // inserting a copy instruction after I. Returns the new instruction.
7910 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7911 MachineFunction *MF = I.getParent()->getParent();
7912 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7913 const bool is64Bit = STI.is64Bit();
7914 const X86InstrInfo *TII = STI.getInstrInfo();
7915
7916 // Create a virtual register for the TLS base address.
7917 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7918 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7919 ? &X86::GR64RegClass
7920 : &X86::GR32RegClass);
7921
7922 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7923 MachineInstr *Next = I.getNextNode();
7924 MachineInstr *Copy =
7925 BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7926 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7927 .addReg(is64Bit ? X86::RAX : X86::EAX);
7928
7929 return Copy;
7930 }
7931
7932 StringRef getPassName() const override {
7933 return "Local Dynamic TLS Access Clean-up";
7934 }
7935
7936 void getAnalysisUsage(AnalysisUsage &AU) const override {
7937 AU.setPreservesCFG();
7938 AU.addRequired<MachineDominatorTree>();
7939 MachineFunctionPass::getAnalysisUsage(AU);
7940 }
7941 };
7942 }
7943
7944 char LDTLSCleanup::ID = 0;
7945 FunctionPass*
7946 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7947
7948 /// Constants defining how certain sequences should be outlined.
7949 ///
7950 /// \p MachineOutlinerDefault implies that the function is called with a call
7951 /// instruction, and a return must be emitted for the outlined function frame.
7952 ///
7953 /// That is,
7954 ///
7955 /// I1 OUTLINED_FUNCTION:
7956 /// I2 --> call OUTLINED_FUNCTION I1
7957 /// I3 I2
7958 /// I3
7959 /// ret
7960 ///
7961 /// * Call construction overhead: 1 (call instruction)
7962 /// * Frame construction overhead: 1 (return instruction)
7963 ///
7964 /// \p MachineOutlinerTailCall implies that the function is being tail called.
7965 /// A jump is emitted instead of a call, and the return is already present in
7966 /// the outlined sequence. That is,
7967 ///
7968 /// I1 OUTLINED_FUNCTION:
7969 /// I2 --> jmp OUTLINED_FUNCTION I1
7970 /// ret I2
7971 /// ret
7972 ///
7973 /// * Call construction overhead: 1 (jump instruction)
7974 /// * Frame construction overhead: 0 (don't need to return)
7975 ///
7976 enum MachineOutlinerClass {
7977 MachineOutlinerDefault,
7978 MachineOutlinerTailCall
7979 };
7980
7981 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7982 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7983 unsigned SequenceSize =
7984 std::accumulate(RepeatedSequenceLocs[0].front(),
7985 std::next(RepeatedSequenceLocs[0].back()), 0,
7986 [](unsigned Sum, const MachineInstr &MI) {
7987 // FIXME: x86 doesn't implement getInstSizeInBytes, so
7988 // we can't tell the cost. Just assume each instruction
7989 // is one byte.
7990 if (MI.isDebugInstr() || MI.isKill())
7991 return Sum;
7992 return Sum + 1;
7993 });
7994
7995 // FIXME: Use real size in bytes for call and ret instructions.
7996 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7997 for (outliner::Candidate &C : RepeatedSequenceLocs)
7998 C.setCallInfo(MachineOutlinerTailCall, 1);
7999
8000 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8001 0, // Number of bytes to emit frame.
8002 MachineOutlinerTailCall // Type of frame.
8003 );
8004 }
8005
8006 for (outliner::Candidate &C : RepeatedSequenceLocs)
8007 C.setCallInfo(MachineOutlinerDefault, 1);
8008
8009 return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8010 MachineOutlinerDefault);
8011 }
8012
8013 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8014 bool OutlineFromLinkOnceODRs) const {
8015 const Function &F = MF.getFunction();
8016
8017 // Does the function use a red zone? If it does, then we can't risk messing
8018 // with the stack.
8019 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8020 // It could have a red zone. If it does, then we don't want to touch it.
8021 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8022 if (!X86FI || X86FI->getUsesRedZone())
8023 return false;
8024 }
8025
8026 // If we *don't* want to outline from things that could potentially be deduped
8027 // then return false.
8028 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8029 return false;
8030
8031 // This function is viable for outlining, so return true.
8032 return true;
8033 }
8034
8035 outliner::InstrType
8036 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
8037 MachineInstr &MI = *MIT;
8038 // Don't allow debug values to impact outlining type.
8039 if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8040 return outliner::InstrType::Invisible;
8041
8042 // At this point, KILL instructions don't really tell us much so we can go
8043 // ahead and skip over them.
8044 if (MI.isKill())
8045 return outliner::InstrType::Invisible;
8046
8047 // Is this a tail call? If yes, we can outline as a tail call.
8048 if (isTailCall(MI))
8049 return outliner::InstrType::Legal;
8050
8051 // Is this the terminator of a basic block?
8052 if (MI.isTerminator() || MI.isReturn()) {
8053
8054 // Does its parent have any successors in its MachineFunction?
8055 if (MI.getParent()->succ_empty())
8056 return outliner::InstrType::Legal;
8057
8058 // It does, so we can't tail call it.
8059 return outliner::InstrType::Illegal;
8060 }
8061
8062 // Don't outline anything that modifies or reads from the stack pointer.
8063 //
8064 // FIXME: There are instructions which are being manually built without
8065 // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8066 // able to remove the extra checks once those are fixed up. For example,
8067 // sometimes we might get something like %rax = POP64r 1. This won't be
8068 // caught by modifiesRegister or readsRegister even though the instruction
8069 // really ought to be formed so that modifiesRegister/readsRegister would
8070 // catch it.
8071 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8072 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8073 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8074 return outliner::InstrType::Illegal;
8075
8076 // Outlined calls change the instruction pointer, so don't read from it.
8077 if (MI.readsRegister(X86::RIP, &RI) ||
8078 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8079 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8080 return outliner::InstrType::Illegal;
8081
8082 // Positions can't safely be outlined.
8083 if (MI.isPosition())
8084 return outliner::InstrType::Illegal;
8085
8086 // Make sure none of the operands of this instruction do anything tricky.
8087 for (const MachineOperand &MOP : MI.operands())
8088 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8089 MOP.isTargetIndex())
8090 return outliner::InstrType::Illegal;
8091
8092 return outliner::InstrType::Legal;
8093 }
8094
8095 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8096 MachineFunction &MF,
8097 const outliner::OutlinedFunction &OF)
8098 const {
8099 // If we're a tail call, we already have a return, so don't do anything.
8100 if (OF.FrameConstructionID == MachineOutlinerTailCall)
8101 return;
8102
8103 // We're a normal call, so our sequence doesn't have a return instruction.
8104 // Add it in.
8105 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
8106 MBB.insert(MBB.end(), retq);
8107 }
8108
8109 MachineBasicBlock::iterator
8110 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
8111 MachineBasicBlock::iterator &It,
8112 MachineFunction &MF,
8113 const outliner::Candidate &C) const {
8114 // Is it a tail call?
8115 if (C.CallConstructionID == MachineOutlinerTailCall) {
8116 // Yes, just insert a JMP.
8117 It = MBB.insert(It,
8118 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
8119 .addGlobalAddress(M.getNamedValue(MF.getName())));
8120 } else {
8121 // No, insert a call.
8122 It = MBB.insert(It,
8123 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
8124 .addGlobalAddress(M.getNamedValue(MF.getName())));
8125 }
8126
8127 return It;
8128 }
8129
8130 #define GET_INSTRINFO_HELPERS
8131 #include "X86GenInstrInfo.inc"
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