test/MC/AMDGPU/vintrp.s

   1 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
   2 // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
   3
   4 v_interp_p1_f32 v1, v0, attr0.x
   5 // SI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xc8]
   6 // VI: v_interp_p1_f32_e32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4]
   7
   8 v_interp_p1_f32 v2, v0, attr0.y
   9 // SI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xc8]
  10 // VI: v_interp_p1_f32_e32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4]
  11
  12 v_interp_p1_f32 v3, v0, attr0.z
  13 // SI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xc8]
  14 // VI: v_interp_p1_f32_e32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4]
  15
  16 v_interp_p1_f32 v4, v0, attr0.w
  17 // SI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xc8]
  18 // VI: v_interp_p1_f32_e32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4]
  19
  20 v_interp_p1_f32 v5, v0, attr0.x
  21 // SI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xc8]
  22 // VI: v_interp_p1_f32_e32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4]
  23
  24 v_interp_p1_f32 v6, v0, attr1.x
  25 // SI: v_interp_p1_f32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xc8]
  26 // VI: v_interp_p1_f32_e32 v6, v0, attr1.x ; encoding: [0x00,0x04,0x18,0xd4]
  27
  28 v_interp_p1_f32 v7, v0, attr2.y
  29 // SI: v_interp_p1_f32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xc8]
  30 // VI: v_interp_p1_f32_e32 v7, v0, attr2.y ; encoding: [0x00,0x09,0x1c,0xd4]
  31
  32 v_interp_p1_f32 v8, v0, attr3.z
  33 // SI: v_interp_p1_f32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xc8]
  34 // VI: v_interp_p1_f32_e32 v8, v0, attr3.z ; encoding: [0x00,0x0e,0x20,0xd4]
  35
  36 v_interp_p1_f32 v9, v0, attr4.w
  37 // SI: v_interp_p1_f32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xc8]
  38 // VI: v_interp_p1_f32_e32 v9, v0, attr4.w ; encoding: [0x00,0x13,0x24,0xd4]
  39
  40 v_interp_p1_f32 v10, v0, attr63.w
  41 // SI: v_interp_p1_f32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xc8]
  42 // VI: v_interp_p1_f32_e32 v10, v0, attr63.w ; encoding: [0x00,0xff,0x28,0xd4]
  43
  44
  45 v_interp_p2_f32 v2, v1, attr0.x
  46 // SI: v_interp_p2_f32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xc8]
  47 // VI: v_interp_p2_f32_e32 v2, v1, attr0.x ; encoding: [0x01,0x00,0x09,0xd4]
  48
  49 v_interp_p2_f32 v3, v1, attr0.y
  50 // SI: v_interp_p2_f32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xc8]
  51 // VI: v_interp_p2_f32_e32 v3, v1, attr0.y ; encoding: [0x01,0x01,0x0d,0xd4]
  52
  53 v_interp_p2_f32 v4, v1, attr0.z
  54 // SI: v_interp_p2_f32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xc8]
  55 // VI: v_interp_p2_f32_e32 v4, v1, attr0.z ; encoding: [0x01,0x02,0x11,0xd4]
  56
  57 v_interp_p2_f32 v5, v1, attr0.w
  58 // SI: v_interp_p2_f32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xc8]
  59 // VI: v_interp_p2_f32_e32 v5, v1, attr0.w ; encoding: [0x01,0x03,0x15,0xd4]
  60
  61 v_interp_p2_f32 v6, v1, attr0.x
  62 // SI: v_interp_p2_f32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xc8]
  63 // VI: v_interp_p2_f32_e32 v6, v1, attr0.x ; encoding: [0x01,0x00,0x19,0xd4]
  64
  65 v_interp_p2_f32 v7, v1, attr1.x
  66 // SI: v_interp_p2_f32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xc8]
  67 // VI: v_interp_p2_f32_e32 v7, v1, attr1.x ; encoding: [0x01,0x04,0x1d,0xd4]
  68
  69 v_interp_p2_f32 v8, v1, attr63.x
  70 // SI: v_interp_p2_f32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xc8]
  71 // VI: v_interp_p2_f32_e32 v8, v1, attr63.x ; encoding: [0x01,0xfc,0x21,0xd4]
  72
  73
  74 v_interp_mov_f32 v0, p10, attr0.x
  75 // SI: v_interp_mov_f32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xc8]
  76 // VI: v_interp_mov_f32_e32 v0, p10, attr0.x ; encoding: [0x00,0x00,0x02,0xd4]
  77
  78 v_interp_mov_f32 v1, p20, attr0.x
  79 // SI: v_interp_mov_f32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xc8]
  80 // VI: v_interp_mov_f32_e32 v1, p20, attr0.x ; encoding: [0x01,0x00,0x06,0xd4]
  81
  82 v_interp_mov_f32 v2, p0, attr0.x
  83 // SI: v_interp_mov_f32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xc8]
  84 // VI: v_interp_mov_f32_e32 v2, p0, attr0.x ; encoding: [0x02,0x00,0x0a,0xd4]
  85
  86 v_interp_mov_f32 v4, p10, attr0.y
  87 // SI: v_interp_mov_f32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xc8]
  88 // VI: v_interp_mov_f32_e32 v4, p10, attr0.y ; encoding: [0x00,0x01,0x12,0xd4]
  89
  90 v_interp_mov_f32 v5, p10, attr0.z
  91 // SI: v_interp_mov_f32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xc8]
  92 // VI: v_interp_mov_f32_e32 v5, p10, attr0.z ; encoding: [0x00,0x02,0x16,0xd4]
  93
  94 v_interp_mov_f32 v6, p10, attr0.w
  95 // SI: v_interp_mov_f32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xc8]
  96 // VI: v_interp_mov_f32_e32 v6, p10, attr0.w ; encoding: [0x00,0x03,0x1a,0xd4]
  97
  98 v_interp_mov_f32 v7, p10, attr0.x
  99 // SI: v_interp_mov_f32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xc8]
 100 // VI: v_interp_mov_f32_e32 v7, p10, attr0.x ; encoding: [0x00,0x00,0x1e,0xd4]
 101
 102 v_interp_mov_f32 v9, p10, attr63.y
 103 // SI: v_interp_mov_f32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xc8]
 104 // VI: v_interp_mov_f32_e32 v9, p10, attr63.y ; encoding: [0x00,0xfd,0x26,0xd4]
 105