test/MC/ARM/invalid-fp-armv8.s

   1 @ RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=V8
   2
   3 @ VCVT{B,T}
   4
   5   vcvtt.f64.f16 d3, s1
   6 @ V7-NOT: vcvtt.f64.f16 d3, s1      @ encoding: [0xe0,0x3b,0xb2,0xee]
   7   vcvtt.f16.f64 s5, d12
   8 @ V7-NOT: vcvtt.f16.f64 s5, d12     @ encoding: [0xcc,0x2b,0xf3,0xee]
   9
  10   vsel.f32 s3, s4, s6
  11 @ V8: error: invalid instruction
  12   vselne.f32 s3, s4, s6
  13 @ V8: error: invalid instruction
  14   vselmi.f32 s3, s4, s6
  15 @ V8: error: invalid instruction
  16   vselpl.f32 s3, s4, s6
  17 @ V8: error: invalid instruction
  18   vselvc.f32 s3, s4, s6
  19 @ V8: error: invalid instruction
  20   vselcs.f32 s3, s4, s6
  21 @ V8: error: invalid instruction
  22   vselcc.f32 s3, s4, s6
  23 @ V8: error: invalid instruction
  24   vselhs.f32 s3, s4, s6
  25 @ V8: error: invalid instruction
  26   vsello.f32 s3, s4, s6
  27 @ V8: error: invalid instruction
  28   vselhi.f32 s3, s4, s6
  29 @ V8: error: invalid instruction
  30   vsells.f32 s3, s4, s6
  31 @ V8: error: invalid instruction
  32   vsellt.f32 s3, s4, s6
  33 @ V8: error: invalid instruction
  34   vselle.f32 s3, s4, s6
  35 @ V8: error: invalid instruction
  36
  37 vseleq.f32 s0, d2, d1
  38 @ V8: error: invalid instruction
  39 vselgt.f64 s3, s2, s1
  40 @ V8: error: invalid operand for instruction
  41 vselgt.f32 s0, q3, q1
  42 @ V8: error: invalid instruction
  43 vselgt.f64 q0, s3, q1
  44 @ V8: error: invalid instruction
  45
  46 vmaxnm.f32 s0, d2, d1
  47 @ V8: error: invalid instruction
  48 vminnm.f64 s3, s2, s1
  49 @ V8: error: invalid operand for instruction
  50 vmaxnm.f32 s0, q3, q1
  51 @ V8: error: invalid instruction
  52 vmaxnm.f64 q0, s3, q1
  53 @ V8: error: invalid instruction
  54 vmaxnmgt.f64 q0, s3, q1
  55 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
  56
  57 vcvta.s32.f64 d3, s2
  58 @ V8: error: invalid instruction
  59 vcvtp.s32.f32 d3, s2
  60 @ V8: error: operand must be a register in range [s0, s31]
  61 vcvtn.u32.f64 d3, s2
  62 @ V8: error: invalid instruction
  63 vcvtm.u32.f32 d3, s2
  64 @ V8: error: operand must be a register in range [s0, s31]
  65 vcvtnge.u32.f64 d3, s2
  66 @ V8: error: instruction 'vcvtn' is not predicable, but condition code specified
  67
  68 vcvtbgt.f64.f16 q0, d3
  69 @ V8: error: invalid instruction
  70 vcvttlt.f64.f16 s0, s3
  71 @ V8: error: invalid instruction, any one of the following would fix this:
  72 @ V8: note: operand must be a register in range [d0, d31]
  73 @ V8: note: invalid operand for instruction
  74 vcvttvs.f16.f64 s0, s3
  75 @ V8: error: invalid instruction, any one of the following would fix this:
  76 @ V8: note: operand must be a register in range [d0, d31]
  77 @ V8: note: invalid operand for instruction
  78 vcvtthi.f16.f64 q0, d3
  79 @ V8: error: operand must be a register in range [s0, s31]
  80
  81 vrintrlo.f32.f32 d3, q0
  82 @ V8: error: invalid instruction
  83 vrintxcs.f32.f32 d3, d0
  84 @ V8: error: invalid instruction
  85
  86 vrinta.f64.f64 s3, q0
  87 @ V8: error: invalid instruction
  88 vrintn.f32.f32 d3, d0
  89 @ V8: error: instruction requires: NEON
  90 vrintp.f32 q3, q0
  91 @ V8: error: instruction requires: NEON
  92 vrintmlt.f32 q3, q0
  93 @ V8: error: instruction 'vrintm' is not predicable, but condition code specified