test/MC/ARM/mve-load-store.s

   1 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s 2>%t \
   2 # RUN:   | FileCheck --check-prefix=CHECK %s
   3 # RUN:     FileCheck --check-prefix=ERROR < %t %s
   4 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t
   5 # RUN:     FileCheck --check-prefix=ERROR-NOMVE < %t %s
   6
   7 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
   8 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
   9 vldrb.u8 q0, [r0]
  10
  11 # CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]
  12 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  13 vldrb.u8 q1, [r0]
  14
  15 # CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]
  16 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  17 vldrb.u8 q0, [r11]
  18
  19 # CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]
  20 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  21 vldrb.u8 q3, [r11]
  22
  23 # CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]
  24 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  25 vldrb.u8 q0, [r4, #56]
  26
  27 # CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]
  28 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  29 vldrb.u8 q4, [r4, #56]
  30
  31 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
  32 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  33 vldrb.u8 q0, [r8, #56]
  34
  35 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
  36 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  37 vldrb.u8 q5, [r4, #56]!
  38
  39 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
  40 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  41 vldrb.u8 q5, [r4, #56]!
  42
  43 # CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]
  44 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  45 vldrb.u8 q5, [r4], #-25
  46
  47 # CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]
  48 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  49 vldrb.u8 q5, [r10], #-25
  50
  51 # CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]
  52 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  53 vldrb.u8 q5, [sp, #-25]
  54
  55 # CHECK: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe]
  56 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  57 vldrb.u8 q5, [sp, #-127]
  58
  59 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
  60 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  61 vldrb.u8 q0, [r0, #128]
  62
  63 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
  64 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  65 vldrb.u8 q0, [r0, #-128]!
  66
  67 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
  68 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  69 vldrb.u8 q0, [r0], #128
  70
  71 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
  72 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  73 vstrb.8 q0, [r0]
  74
  75 # CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]
  76 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  77 vstrb.8 q1, [r0]
  78
  79 # CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]
  80 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  81 vstrb.8 q0, [r11]
  82
  83 # CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]
  84 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  85 vstrb.8 q3, [r11]
  86
  87 # CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]
  88 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  89 vstrb.8 q0, [r4, #56]
  90
  91 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
  92 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  93 vstrb.8 q4, [r4, #56]
  94
  95 # CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]
  96 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
  97 vstrb.8 q0, [r8, #56]
  98
  99 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
 100 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 101 vstrb.8 q5, [r4, #56]!
 102
 103 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
 104 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 105 vstrb.8 q5, [r4, #56]!
 106
 107 # CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]
 108 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 109 vstrb.8 q5, [r4], #-25
 110
 111 # CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]
 112 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 113 vstrb.8 q5, [r10], #-25
 114
 115 # CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]
 116 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 117 vstrb.8 q5, [sp, #-25]
 118
 119 # CHECK: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe]
 120 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 121 vstrb.8 q5, [sp, #127]
 122
 123 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 124 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 125 vstrb.u8 q0, [r0, #128]
 126
 127 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 128 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 129 vstrb.u8 q0, [r0, #-128]!
 130
 131 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 132 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 133 vstrb.u8 q0, [r0], #128
 134
 135 # CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]
 136 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 137 vldrb.u16 q0, [r0]
 138
 139 # CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]
 140 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 141 vldrb.u16 q1, [r0]
 142
 143 # CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]
 144 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 145 vldrb.u16 q0, [r7]
 146
 147 # CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]
 148 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 149 vldrb.u16 q3, [r7]
 150
 151 # CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]
 152 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 153 vldrb.u16 q0, [r4, #56]
 154
 155 # CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]
 156 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 157 vldrb.u16 q4, [r4, #56]
 158
 159 # CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]
 160 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 161 vldrb.u16 q0, [r2, #56]
 162
 163 # CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
 164 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 165 vldrb.u16 q5, [r4, #56]!
 166
 167 # CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
 168 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 169 vldrb.u16 q5, [r4, #56]!
 170
 171 # CHECK: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae]
 172 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 173 vldrb.u16 q5, [r4], #-1
 174
 175 # CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]
 176 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 177 vldrb.u16 q5, [r3], #-25
 178
 179 # CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]
 180 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 181 vldrb.u16 q5, [r6, #-25]
 182
 183 # CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]
 184 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 185 vldrb.u16 q5, [r6, #-64]
 186
 187 # CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]
 188 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 189 vldrb.s16 q0, [r0]
 190
 191 # CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]
 192 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 193 vldrb.s16 q1, [r0]
 194
 195 # CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]
 196 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 197 vldrb.s16 q0, [r7]
 198
 199 # CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]
 200 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 201 vldrb.s16 q3, [r7]
 202
 203 # CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]
 204 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 205 vldrb.s16 q0, [r4, #56]
 206
 207 # CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]
 208 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 209 vldrb.s16 q4, [r4, #56]
 210
 211 # CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]
 212 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 213 vldrb.s16 q0, [r2, #56]
 214
 215 # CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
 216 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 217 vldrb.s16 q5, [r4, #56]!
 218
 219 # CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
 220 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 221 vldrb.s16 q5, [r4, #56]!
 222
 223 # CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]
 224 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 225 vldrb.s16 q5, [r4], #-25
 226
 227 # CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]
 228 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 229 vldrb.s16 q5, [r3], #-25
 230
 231 # CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]
 232 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 233 vldrb.s16 q5, [r6, #-25]
 234
 235 # CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]
 236 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 237 vldrb.s16 q5, [r6, #-64]
 238
 239 # CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]
 240 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 241 vstrb.16 q0, [r0]
 242
 243 # CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]
 244 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 245 vstrb.16 q1, [r0]
 246
 247 # CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]
 248 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 249 vstrb.16 q0, [r7]
 250
 251 # CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]
 252 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 253 vstrb.16 q3, [r7]
 254
 255 # CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]
 256 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 257 vstrb.16 q0, [r4, #56]
 258
 259 # CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]
 260 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 261 vstrb.16 q4, [r4, #56]
 262
 263 # CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]
 264 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 265 vstrb.16 q0, [r5, #56]
 266
 267 # CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
 268 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 269 vstrb.16 q5, [r4, #56]!
 270
 271 # CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
 272 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 273 vstrb.16 q5, [r4, #56]!
 274
 275 # CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]
 276 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 277 vstrb.16 q5, [r4], #-25
 278
 279 # CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]
 280 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 281 vstrb.16 q5, [r3], #-25
 282
 283 # CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]
 284 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 285 vstrb.16 q5, [r2, #-25]
 286
 287 # CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]
 288 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 289 vstrb.16 q5, [r2, #-64]
 290
 291 # CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
 292 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 293 vldrb.u32 q0, [r0]
 294
 295 # CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]
 296 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 297 vldrb.u32 q1, [r0]
 298
 299 # CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]
 300 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 301 vldrb.u32 q0, [r7]
 302
 303 # CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]
 304 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 305 vldrb.u32 q3, [r7]
 306
 307 # CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]
 308 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 309 vldrb.u32 q0, [r4, #56]
 310
 311 # CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]
 312 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 313 vldrb.u32 q4, [r4, #56]
 314
 315 # CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]
 316 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 317 vldrb.u32 q0, [r2, #56]
 318
 319 # CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
 320 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 321 vldrb.u32 q5, [r4, #56]!
 322
 323 # CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
 324 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 325 vldrb.u32 q5, [r4, #56]!
 326
 327 # CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]
 328 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 329 vldrb.u32 q5, [r4], #-25
 330
 331 # CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]
 332 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 333 vldrb.u32 q5, [r3], #-25
 334
 335 # CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]
 336 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 337 vldrb.u32 q5, [r6, #-25]
 338
 339 # CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]
 340 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 341 vldrb.u32 q5, [r6, #-64]
 342
 343 # CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]
 344 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 345 vldrb.s32 q0, [r0]
 346
 347 # CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]
 348 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 349 vldrb.s32 q1, [r0]
 350
 351 # CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]
 352 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 353 vldrb.s32 q0, [r7]
 354
 355 # CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]
 356 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 357 vldrb.s32 q3, [r7]
 358
 359 # CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]
 360 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 361 vldrb.s32 q0, [r4, #56]
 362
 363 # CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]
 364 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 365 vldrb.s32 q4, [r4, #56]
 366
 367 # CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]
 368 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 369 vldrb.s32 q0, [r2, #56]
 370
 371 # CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
 372 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 373 vldrb.s32 q5, [r4, #56]!
 374
 375 # CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
 376 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 377 vldrb.s32 q5, [r4, #56]!
 378
 379 # CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]
 380 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 381 vldrb.s32 q5, [r4], #-25
 382
 383 # CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]
 384 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 385 vldrb.s32 q5, [r3], #-25
 386
 387 # CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]
 388 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 389 vldrb.s32 q5, [r6, #-25]
 390
 391 # CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]
 392 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 393 vldrb.s32 q5, [r6, #-64]
 394
 395 # CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]
 396 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 397 vstrb.32 q0, [r0]
 398
 399 # CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]
 400 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 401 vstrb.32 q1, [r0]
 402
 403 # CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]
 404 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 405 vstrb.32 q0, [r7]
 406
 407 # CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]
 408 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 409 vstrb.32 q3, [r7]
 410
 411 # CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]
 412 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 413 vstrb.32 q0, [r4, #56]
 414
 415 # CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]
 416 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 417 vstrb.32 q4, [r4, #56]
 418
 419 # CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]
 420 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 421 vstrb.32 q0, [r5, #56]
 422
 423 # CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
 424 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 425 vstrb.32 q5, [r4, #56]!
 426
 427 # CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
 428 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 429 vstrb.32 q5, [r4, #56]!
 430
 431 # CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]
 432 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 433 vstrb.32 q5, [r4], #-25
 434
 435 # CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]
 436 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 437 vstrb.32 q5, [r3], #-25
 438
 439 # CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]
 440 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 441 vstrb.32 q5, [r2, #-25]
 442
 443 # CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]
 444 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 445 vstrb.32 q5, [r2, #-64]
 446
 447 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
 448 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 449 vldrh.u16 q0, [r0]
 450
 451 # CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]
 452 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 453 vldrh.u16 q1, [r0]
 454
 455 # CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]
 456 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 457 vldrh.u16 q0, [r11]
 458
 459 # CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]
 460 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 461 vldrh.u16 q3, [r11]
 462
 463 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
 464 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 465 vldrh.u16 q0, [r4, #56]
 466
 467 # CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]
 468 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 469 vldrh.u16 q4, [r4, #56]
 470
 471 # CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]
 472 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 473 vldrh.u16 q0, [r8, #56]
 474
 475 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
 476 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 477 vldrh.u16 q5, [r4, #56]!
 478
 479 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
 480 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 481 vldrh.u16 q5, [r4, #56]!
 482
 483 # CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]
 484 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 485 vldrh.u16 q5, [r4], #-26
 486
 487 # CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]
 488 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 489 vldrh.u16 q5, [r10], #-26
 490
 491 # CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]
 492 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 493 vldrh.u16 q5, [sp, #-26]
 494
 495 # CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]
 496 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 497 vldrh.u16 q5, [sp, #-64]
 498
 499 # CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]
 500 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 501 vldrh.u16 q5, [sp, #-254]
 502
 503 # CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]
 504 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 505 vldrh.u16 q5, [r10], #254
 506
 507 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
 508 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 509 vstrh.16 q0, [r0]
 510
 511 # CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]
 512 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 513 vstrh.16 q1, [r0]
 514
 515 # CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]
 516 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 517 vstrh.16 q0, [r11]
 518
 519 # CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]
 520 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 521 vstrh.16 q3, [r11]
 522
 523 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
 524 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 525 vstrh.16 q0, [r4, #56]
 526
 527 # CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]
 528 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 529 vstrh.16 q4, [r4, #56]
 530
 531 # CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]
 532 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 533 vstrh.16 q0, [r8, #56]
 534
 535 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
 536 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 537 vstrh.16 q5, [r4, #56]!
 538
 539 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
 540 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 541 vstrh.16 q5, [r4, #56]!
 542
 543 # CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]
 544 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 545 vstrh.16 q5, [r4], #-26
 546
 547 # CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]
 548 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 549 vstrh.16 q5, [r10], #-26
 550
 551 # CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]
 552 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 553 vstrh.16 q5, [sp, #-26]
 554
 555 # CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]
 556 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 557 vstrh.16 q5, [sp, #-64]
 558
 559 # CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]
 560 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 561 vstrh.16 q5, [sp, #-254]
 562
 563 # CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]
 564 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 565 vstrh.16 q5, [r10], #254
 566
 567 # CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]
 568 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 569 vldrh.u32 q0, [r0]
 570
 571 # CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]
 572 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 573 vldrh.u32 q1, [r0]
 574
 575 # CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]
 576 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 577 vldrh.u32 q0, [r7]
 578
 579 # CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]
 580 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 581 vldrh.u32 q3, [r7]
 582
 583 # CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]
 584 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 585 vldrh.u32 q0, [r4, #56]
 586
 587 # CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]
 588 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 589 vldrh.u32 q4, [r4, #56]
 590
 591 # CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]
 592 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 593 vldrh.u32 q0, [r2, #56]
 594
 595 # CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
 596 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 597 vldrh.u32 q5, [r4, #56]!
 598
 599 # CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
 600 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 601 vldrh.u32 q5, [r4, #56]!
 602
 603 # CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]
 604 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 605 vldrh.u32 q5, [r4], #-26
 606
 607 # CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]
 608 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 609 vldrh.u32 q5, [r3], #-26
 610
 611 # CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]
 612 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 613 vldrh.u32 q5, [r6, #-26]
 614
 615 # CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]
 616 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 617 vldrh.u32 q5, [r6, #-64]
 618
 619 # CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]
 620 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 621 vldrh.u32 q5, [r6, #-254]
 622
 623 # CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]
 624 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 625 vldrh.u32 q5, [r4, #254]!
 626
 627 # CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]
 628 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 629 vldrh.s32 q0, [r0]
 630
 631 # CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]
 632 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 633 vldrh.s32 q1, [r0]
 634
 635 # CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]
 636 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 637 vldrh.s32 q0, [r7]
 638
 639 # CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]
 640 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 641 vldrh.s32 q3, [r7]
 642
 643 # CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]
 644 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 645 vldrh.s32 q0, [r4, #56]
 646
 647 # CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]
 648 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 649 vldrh.s32 q4, [r4, #56]
 650
 651 # CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]
 652 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 653 vldrh.s32 q0, [r2, #56]
 654
 655 # CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
 656 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 657 vldrh.s32 q5, [r4, #56]!
 658
 659 # CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
 660 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 661 vldrh.s32 q5, [r4, #56]!
 662
 663 # CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]
 664 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 665 vldrh.s32 q5, [r4], #-26
 666
 667 # CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]
 668 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 669 vldrh.s32 q5, [r3], #-26
 670
 671 # CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]
 672 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 673 vldrh.s32 q5, [r6, #-26]
 674
 675 # CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]
 676 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 677 vldrh.s32 q5, [r6, #-64]
 678
 679 # CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]
 680 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 681 vldrh.s32 q5, [r6, #-254]
 682
 683 # CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]
 684 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 685 vldrh.s32 q5, [r4, #254]!
 686
 687 # CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]
 688 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 689 vstrh.32 q0, [r0]
 690
 691 # CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]
 692 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 693 vstrh.32 q1, [r0]
 694
 695 # CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]
 696 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 697 vstrh.32 q0, [r7]
 698
 699 # CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]
 700 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 701 vstrh.32 q3, [r7]
 702
 703 # CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]
 704 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 705 vstrh.32 q0, [r4, #56]
 706
 707 # CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]
 708 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 709 vstrh.32 q4, [r4, #56]
 710
 711 # CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]
 712 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 713 vstrh.32 q0, [r5, #56]
 714
 715 # CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
 716 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 717 vstrh.32 q5, [r4, #56]!
 718
 719 # CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
 720 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 721 vstrh.32 q5, [r4, #56]!
 722
 723 # CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]
 724 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 725 vstrh.32 q5, [r4], #-26
 726
 727 # CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]
 728 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 729 vstrh.32 q5, [r3], #-26
 730
 731 # CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]
 732 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 733 vstrh.32 q5, [r2, #-26]
 734
 735 # CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]
 736 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 737 vstrh.32 q5, [r2, #-64]
 738
 739 # CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]
 740 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 741 vstrh.32 q5, [r2, #-254]
 742
 743 # CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]
 744 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 745 vstrh.32 q5, [r4, #254]!
 746
 747 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
 748 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 749 vldrw.u32 q0, [r0]
 750
 751 # CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]
 752 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 753 vldrw.u32 q1, [r0]
 754
 755 # CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]
 756 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 757 vldrw.u32 q0, [r11]
 758
 759 # CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]
 760 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 761 vldrw.u32 q3, [r11]
 762
 763 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
 764 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 765 vldrw.u32 q0, [r4, #56]
 766
 767 # CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]
 768 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 769 vldrw.u32 q4, [r4, #56]
 770
 771 # CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]
 772 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 773 vldrw.u32 q0, [r8, #56]
 774
 775 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
 776 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 777 vldrw.u32 q5, [r4, #56]!
 778
 779 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
 780 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 781 vldrw.u32 q5, [r4, #56]!
 782
 783 # CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]
 784 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 785 vldrw.u32 q5, [r4], #-28
 786
 787 # CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]
 788 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 789 vldrw.u32 q5, [r10], #-28
 790
 791 # CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]
 792 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 793 vldrw.u32 q5, [sp, #-28]
 794
 795 # CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]
 796 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 797 vldrw.u32 q5, [sp, #-64]
 798
 799 # CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]
 800 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 801 vldrw.u32 q5, [sp, #-508]
 802
 803 # CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]
 804 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 805 vldrw.u32 q5, [r4, #508]!
 806
 807 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
 808 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 809 vstrw.32 q0, [r0]
 810
 811 # CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]
 812 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 813 vstrw.32 q1, [r0]
 814
 815 # CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]
 816 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 817 vstrw.32 q0, [r11]
 818
 819 # CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]
 820 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 821 vstrw.32 q3, [r11]
 822
 823 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
 824 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 825 vstrw.32 q0, [r4, #56]
 826
 827 # CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]
 828 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 829 vstrw.32 q4, [r4, #56]
 830
 831 # CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]
 832 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 833 vstrw.32 q0, [r8, #56]
 834
 835 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
 836 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 837 vstrw.32 q5, [r4, #56]!
 838
 839 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
 840 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 841 vstrw.32 q5, [r4, #56]!
 842
 843 # CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]
 844 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 845 vstrw.32 q5, [r4], #-28
 846
 847 # CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]
 848 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 849 vstrw.32 q5, [r10], #-28
 850
 851 # CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]
 852 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 853 vstrw.32 q5, [sp, #-28]
 854
 855 # CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]
 856 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 857 vstrw.32 q5, [sp, #-64]
 858
 859 # CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]
 860 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 861 vstrw.32 q5, [sp, #-508]
 862
 863 # CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]
 864 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 865 vstrw.32 q5, [r4, #508]!
 866
 867 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 868 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 869 vstrb.16 q0, [r8]
 870
 871 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 872 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 873 vldrh.u32 q0, [r8]
 874
 875 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 876 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 877 vstrw.32 q5, [sp, #-64]!
 878
 879 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 880 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 881 vstrw.32 q5, [sp, #-3]
 882
 883 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
 884 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 885 vstrw.32 q5, [sp, #512]
 886
 887 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
 888 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 889 vldrb.u8 q0, [r0, q1]
 890
 891 # CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]
 892 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 893 vldrb.u8 q3, [r10, q1]
 894
 895 # CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]
 896 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 897 vldrb.u16 q0, [r0, q1]
 898
 899 # CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]
 900 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 901 vldrb.u16 q3, [r9, q1]
 902
 903 # CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]
 904 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 905 vldrb.s16 q0, [r0, q1]
 906
 907 # CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]
 908 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 909 vldrb.s16 q3, [sp, q1]
 910
 911 # CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]
 912 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 913 vldrb.u32 q0, [r0, q1]
 914
 915 # CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]
 916 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 917 vldrb.u32 q3, [r0, q1]
 918
 919 # CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]
 920 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 921 vldrb.s32 q0, [r0, q1]
 922
 923 # CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]
 924 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 925 vldrb.s32 q3, [r0, q1]
 926
 927 # CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]
 928 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 929 vldrh.u16 q0, [r0, q1]
 930
 931 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
 932 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 933 vldrh.u16 q3, [r0, q1]
 934
 935 # CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]
 936 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 937 vldrh.u32 q0, [r0, q1]
 938
 939 # CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]
 940 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 941 vldrh.u32 q3, [r0, q1]
 942
 943 # CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]
 944 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 945 vldrh.s32 q0, [r0, q1]
 946
 947 # CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]
 948 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 949 vldrh.s32 q3, [r0, q1]
 950
 951 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 952 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 953 vldrb.u8 q0, [r0, q0]
 954
 955 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 956 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 957 vldrb.u16 q0, [r0, q0]
 958
 959 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 960 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 961 vldrb.s16 q0, [r0, q0]
 962
 963 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 964 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 965 vldrb.u32 q0, [r0, q0]
 966
 967 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 968 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 969 vldrb.s32 q0, [r0, q0]
 970
 971 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 972 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 973 vldrh.u16 q0, [r0, q0]
 974
 975 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 976 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 977 vldrh.u32 q0, [r0, q0]
 978
 979 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 980 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 981 vldrh.s32 q0, [r0, q0]
 982
 983 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 984 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 985 vldrh.u16 q0, [r0, q0, uxtw #1]
 986
 987 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 988 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 989 vldrh.u32 q0, [r0, q0, uxtw #1]
 990
 991 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 992 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 993 vldrh.s32 q0, [r0, q0, uxtw #1]
 994
 995 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
 996 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
 997 vldrw.u32 q0, [r0, q0]
 998
 999 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
1000 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1001 vldrw.u32 q0, [r0, q0, uxtw #2]
1002
1003 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
1004 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1005 vldrd.u64 q0, [r0, q0]
1006
1007 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
1008 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1009 vldrd.u64 q0, [r0, q0, uxtw #3]
1010
1011 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1012 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1013 vldrh.u16 q0, [r0, q1, uxtw #1]
1014
1015 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1016 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1017 vldrw.u32 q0, [r0, q1]
1018
1019 # CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]
1020 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1021 vldrw.u32 q3, [r0, q1]
1022
1023 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1024 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1025 vldrw.u32 q0, [r0, q1, uxtw #2]
1026
1027 # CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]
1028 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1029 vldrw.u32 q0, [sp, q1, uxtw #2]
1030
1031 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1032 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1033 vldrd.u64 q0, [r0, q1]
1034
1035 # CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]
1036 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1037 vldrd.u64 q3, [r0, q1]
1038
1039 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1040 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1041 vldrd.u64 q0, [r0, q1, uxtw #3]
1042
1043 # CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]
1044 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1045 vldrd.u64 q0, [sp, q1, uxtw #3]
1046
1047 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1048 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1049 vstrb.8 q0, [r0, q1]
1050
1051 # CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]
1052 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1053 vstrb.8 q3, [r10, q1]
1054
1055 # CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]
1056 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1057 vstrb.8 q3, [r0, q3]
1058
1059 # CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]
1060 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1061 vstrb.16 q0, [r0, q1]
1062
1063 # CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]
1064 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1065 vstrb.16 q3, [sp, q1]
1066
1067 # CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]
1068 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1069 vstrb.16 q3, [r0, q3]
1070
1071 # CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]
1072 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1073 vstrb.32 q0, [r0, q1]
1074
1075 # CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]
1076 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1077 vstrb.32 q3, [r0, q1]
1078
1079 # CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]
1080 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1081 vstrb.32 q3, [r0, q3]
1082
1083 # CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]
1084 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1085 vstrh.16 q0, [r0, q1]
1086
1087 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1088 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1089 vstrh.16 q3, [r0, q1]
1090
1091 # CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]
1092 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1093 vstrh.16 q3, [r0, q3]
1094
1095 # CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]
1096 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1097 vstrh.32 q0, [r0, q1]
1098
1099 # CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]
1100 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1101 vstrh.32 q3, [r0, q1]
1102
1103 # CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]
1104 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1105 vstrh.32 q3, [r0, q3]
1106
1107 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1108 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1109 vstrh.16 q0, [r0, q1, uxtw #1]
1110
1111 # CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]
1112 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1113 vstrh.32 q3, [r8, q3, uxtw #1]
1114
1115 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1116 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1117 vstrw.32 q0, [r0, q1]
1118
1119 # CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]
1120 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1121 vstrw.32 q3, [r0, q1]
1122
1123 # CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]
1124 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1125 vstrw.32 q3, [r0, q3]
1126
1127 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1128 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1129 vstrw.32 q0, [r0, q1, uxtw #2]
1130
1131 # CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]
1132 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1133 vstrw.32 q0, [sp, q1, uxtw #2]
1134
1135 # CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]
1136 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1137 vstrd.64 q0, [r0, q1]
1138
1139 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1140 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1141 vstrd.64 q3, [r0, q1]
1142
1143 # CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]
1144 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1145 vstrd.64 q3, [r0, q3]
1146
1147 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1148 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1149 vstrd.64 q0, [r0, q1, uxtw #3]
1150
1151 # CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]
1152 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1153 vstrd.64 q0, [sp, q1, uxtw #3]
1154
1155 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1156 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1157 vstrw.32 q9, [sp, q1, uxtw #2]
1158
1159 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1160 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1161 vstrh.16 q3, [pc, q1]
1162
1163 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1164 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1165 vstrd.64 q0, [r0, q1, uxtw #1]
1166
1167 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1168 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1169 vldrd.u64 q0, [r0, q1, uxtw #1]
1170
1171 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1172 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1173 vstrd.64 q0, [r0, q1, uxtw #2]
1174
1175 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1176 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1177 vldrd.u64 q0, [r0, q1, uxtw #2]
1178
1179 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1180 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1181 vldrw.u32 q0, [r0, q1, uxtw #1]
1182
1183 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1184 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1185 vstrh.16 q0, [r0, q1, uxtw #2]
1186
1187 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1188 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1189 vstrb.32 q0, [r11, q1, uxtw #1]
1190
1191 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1192 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1193 vldrw.u32 q0, [q1]
1194
1195 # CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]
1196 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1197 vldrw.u32 q7, [q1]
1198
1199 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1200 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1201 vldrw.u32 q7, [q1]!
1202
1203 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1204 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1205 vldrw.u32 q7, [q1, #4]
1206
1207 # CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]
1208 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1209 vldrw.u32 q7, [q1, #-4]
1210
1211 # CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]
1212 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1213 vldrw.u32 q7, [q1, #508]
1214
1215 # CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]
1216 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1217 vldrw.u32 q7, [q1, #-508]
1218
1219 # CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]
1220 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1221 vldrw.u32 q7, [q1, #264]
1222
1223 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1224 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1225 vldrw.u32 q7, [q1, #4]!
1226
1227 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1228 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1229 vstrw.32 q0, [q1]
1230
1231 # CHECK: vstrw.32 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3e]
1232 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1233 vstrw.32 q1, [q1]
1234
1235 # CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]
1236 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1237 vstrw.32 q7, [q1]
1238
1239 # CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
1240 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1241 vstrw.32 q7, [q1]!
1242
1243 # CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]
1244 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1245 vstrw.32 q7, [q7]
1246
1247 # CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]
1248 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1249 vstrw.32 q7, [q1, #4]
1250
1251 # CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]
1252 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1253 vstrw.32 q7, [q1, #-4]
1254
1255 # CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
1256 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1257 vstrw.32 q7, [q1, #508]
1258
1259 # CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]
1260 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1261 vstrw.32 q7, [q1, #-508]
1262
1263 # CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1264 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1265 vstrw.32 q7, [q1, #264]!
1266
1267 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1268 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1269 vstrw.32 q8, [q1]!
1270
1271 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1272 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1273 vstrw.32 q4, [q1, #3]!
1274
1275 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1276 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1277 vldrw.u32 q7, [q1, #512]
1278
1279 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical
1280 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1281 vldrw.32 q1, [q1, #264]
1282
1283 # CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
1284 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1285 vldrd.u64 q0, [q1]
1286
1287 # CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]
1288 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1289 vldrd.u64 q7, [q1]
1290
1291 # CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
1292 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1293 vldrd.u64 q7, [q1]!
1294
1295 # CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
1296 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1297 vldrd.u64 q7, [q1, #8]
1298
1299 # CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]
1300 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1301 vldrd.u64 q7, [q1, #-8]
1302
1303 # CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]
1304 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1305 vldrd.u64 q7, [q1, #1016]
1306
1307 # CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]
1308 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1309 vldrd.u64 q7, [q1, #-1016]
1310
1311 # CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
1312 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1313 vldrd.u64 q7, [q1, #264]
1314
1315 # CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]
1316 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1317 vldrd.u64 q7, [q1, #624]
1318
1319 # CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
1320 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1321 vldrd.u64 q7, [q1, #264]
1322
1323 # CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
1324 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1325 vldrd.u64 q7, [q1, #-1016]!
1326
1327 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical
1328 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1329 vldrd.u64 q6, [q6]
1330
1331 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
1332 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1333 vstrd.64 q0, [q1]
1334
1335 # CHECK: vstrd.64 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3f]
1336 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1337 vstrd.64 q1, [q1]
1338
1339 # CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]
1340 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1341 vstrd.64 q7, [q1]
1342
1343 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
1344 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1345 vstrd.64 q7, [q1]!
1346
1347 # CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]
1348 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1349 vstrd.64 q7, [q7]
1350
1351 # CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]
1352 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1353 vstrd.64 q7, [q1, #8]
1354
1355 # CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
1356 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1357 vstrd.64 q7, [q1, #-8]!
1358
1359 # CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
1360 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1361 vstrd.64 q7, [q1, #1016]
1362
1363 # CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]
1364 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1365 vstrd.64 q7, [q1, #-1016]
1366
1367 # CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
1368 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1369 vstrd.64 q7, [q1, #264]
1370
1371 # CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]
1372 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1373 vstrd.64 q7, [q1, #624]
1374
1375 # CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
1376 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1377 vstrd.64 q7, [q1, #264]
1378
1379 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1380 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1381 vldrd.u64 q8, [q1]!
1382
1383 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1384 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1385 vstrd.64 q7, [q1, #1024]
1386
1387 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1388 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1389 vstrd.64 q4, [q1, #3]
1390
1391 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1392 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1393 vstrd.64 q4, [q1, #4]
1394
1395 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
1396 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1397 vldrb.s8 q0, [r0]
1398
1399 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
1400 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1401 vldrb.8 q0, [r0]
1402
1403 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
1404 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1405 vldrb.s8 q0, [r8, #56]
1406
1407 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
1408 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1409 vldrb.8 q0, [r8, #56]
1410
1411 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
1412 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1413 vldrb.s8 q5, [r4, #56]!
1414
1415 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
1416 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1417 vldrb.8 q5, [r4, #56]!
1418
1419 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
1420 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1421 vstrb.u8 q0, [r0]
1422
1423 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
1424 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1425 vstrb.s8 q0, [r0]
1426
1427 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
1428 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1429 vstrb.u8 q4, [r4, #56]
1430
1431 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
1432 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1433 vstrb.s8 q4, [r4, #56]
1434
1435 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
1436 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1437 vstrb.u8 q5, [r4, #56]!
1438
1439 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
1440 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1441 vstrb.s8 q5, [r4, #56]!
1442
1443 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1444 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1445 vldrh.s16 q0, [r0]
1446
1447 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1448 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1449 vldrh.f16 q0, [r0]
1450
1451 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1452 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1453 vldrh.16 q0, [r0]
1454
1455 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1456 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1457 vldrh.s16 q0, [r4, #56]
1458
1459 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1460 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1461 vldrh.f16 q0, [r4, #56]
1462
1463 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1464 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1465 vldrh.16 q0, [r4, #56]
1466
1467 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1468 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1469 vldrh.s16 q5, [r4, #56]!
1470
1471 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1472 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1473 vldrh.f16 q5, [r4, #56]!
1474
1475 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1476 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1477 vldrh.16 q5, [r4, #56]!
1478
1479 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1480 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1481 vstrh.u16 q0, [r0]
1482
1483 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1484 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1485 vstrh.s16 q0, [r0]
1486
1487 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1488 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1489 vstrh.f16 q0, [r0]
1490
1491 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1492 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1493 vstrh.u16 q0, [r4, #56]
1494
1495 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1496 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1497 vstrh.s16 q0, [r4, #56]
1498
1499 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1500 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1501 vstrh.f16 q0, [r4, #56]
1502
1503 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1504 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1505 vstrh.u16 q5, [r4, #56]!
1506
1507 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1508 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1509 vstrh.s16 q5, [r4, #56]!
1510
1511 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1512 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1513 vstrh.f16 q5, [r4, #56]!
1514
1515 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1516 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1517 vldrw.s32 q0, [r0]
1518
1519 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1520 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1521 vldrw.f32 q0, [r0]
1522
1523 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1524 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1525 vldrw.32 q0, [r0]
1526
1527 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1528 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1529 vldrw.s32 q0, [r4, #56]
1530
1531 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1532 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1533 vldrw.f32 q0, [r4, #56]
1534
1535 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1536 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1537 vldrw.32 q0, [r4, #56]
1538
1539 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1540 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1541 vldrw.s32 q5, [r4, #56]!
1542
1543 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1544 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1545 vldrw.f32 q5, [r4, #56]!
1546
1547 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1548 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1549 vldrw.32 q5, [r4, #56]!
1550
1551 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1552 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1553 vstrw.u32 q0, [r0]
1554
1555 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1556 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1557 vstrw.s32 q0, [r0]
1558
1559 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1560 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1561 vstrw.f32 q0, [r0]
1562
1563 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1564 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1565 vstrw.u32 q0, [r4, #56]
1566
1567 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1568 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1569 vstrw.s32 q0, [r4, #56]
1570
1571 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1572 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1573 vstrw.f32 q0, [r4, #56]
1574
1575 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1576 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1577 vstrw.u32 q5, [r4, #56]!
1578
1579 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1580 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1581 vstrw.s32 q5, [r4, #56]!
1582
1583 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1584 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1585 vstrw.f32 q5, [r4, #56]!
1586
1587 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
1588 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1589 vldrb.s8 q0, [r0, q1]
1590
1591 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
1592 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1593 vldrb.8 q0, [r0, q1]
1594
1595 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1596 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1597 vldrh.s16 q3, [r0, q1]
1598
1599 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1600 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1601 vldrh.f16 q3, [r0, q1]
1602
1603 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1604 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1605 vldrh.16 q3, [r0, q1]
1606
1607 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1608 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1609 vldrh.s16 q0, [r0, q1, uxtw #1]
1610
1611 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1612 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1613 vldrh.f16 q0, [r0, q1, uxtw #1]
1614
1615 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1616 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1617 vldrh.16 q0, [r0, q1, uxtw #1]
1618
1619 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1620 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1621 vldrw.s32 q0, [r0, q1]
1622
1623 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1624 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1625 vldrw.f32 q0, [r0, q1]
1626
1627 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1628 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1629 vldrw.32 q0, [r0, q1]
1630
1631 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1632 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1633 vldrw.s32 q0, [r0, q1, uxtw #2]
1634
1635 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1636 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1637 vldrw.f32 q0, [r0, q1, uxtw #2]
1638
1639 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1640 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1641 vldrw.32 q0, [r0, q1, uxtw #2]
1642
1643 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1644 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1645 vldrd.s64 q0, [r0, q1]
1646
1647 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1648 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1649 vldrd.f64 q0, [r0, q1]
1650
1651 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1652 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1653 vldrd.64 q0, [r0, q1]
1654
1655 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1656 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1657 vldrd.s64 q0, [r0, q1, uxtw #3]
1658
1659 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1660 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1661 vldrd.f64 q0, [r0, q1, uxtw #3]
1662
1663 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1664 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1665 vldrd.64 q0, [r0, q1, uxtw #3]
1666
1667 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1668 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1669 vstrb.u8 q0, [r0, q1]
1670
1671 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1672 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1673 vstrb.s8 q0, [r0, q1]
1674
1675 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1676 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1677 vstrh.u16 q3, [r0, q1]
1678
1679 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1680 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1681 vstrh.s16 q3, [r0, q1]
1682
1683 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1684 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1685 vstrh.f16 q3, [r0, q1]
1686
1687 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1688 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1689 vstrh.u16 q0, [r0, q1, uxtw #1]
1690
1691 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1692 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1693 vstrh.s16 q0, [r0, q1, uxtw #1]
1694
1695 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1696 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1697 vstrh.f16 q0, [r0, q1, uxtw #1]
1698
1699 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1700 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1701 vstrw.u32 q0, [r0, q1]
1702
1703 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1704 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1705 vstrw.s32 q0, [r0, q1]
1706
1707 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1708 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1709 vstrw.f32 q0, [r0, q1]
1710
1711 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1712 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1713 vstrw.u32 q0, [r0, q1, uxtw #2]
1714
1715 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1716 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1717 vstrw.s32 q0, [r0, q1, uxtw #2]
1718
1719 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1720 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1721 vstrw.f32 q0, [r0, q1, uxtw #2]
1722
1723 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1724 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1725 vstrd.u64 q3, [r0, q1]
1726
1727 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1728 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1729 vstrd.s64 q3, [r0, q1]
1730
1731 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1732 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1733 vstrd.f64 q3, [r0, q1]
1734
1735 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1736 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1737 vstrd.u64 q0, [r0, q1, uxtw #3]
1738
1739 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1740 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1741 vstrd.s64 q0, [r0, q1, uxtw #3]
1742
1743 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1744 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1745 vstrd.f64 q0, [r0, q1, uxtw #3]
1746
1747 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1748 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1749 vldrw.s32 q0, [q1]
1750
1751 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1752 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1753 vldrw.f32 q0, [q1]
1754
1755 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1756 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1757 vldrw.32 q0, [q1]
1758
1759 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1760 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1761 vldrw.s32 q7, [q1]!
1762
1763 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1764 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1765 vldrw.f32 q7, [q1]!
1766
1767 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1768 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1769 vldrw.32 q7, [q1]!
1770
1771 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1772 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1773 vldrw.s32 q7, [q1, #4]
1774
1775 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1776 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1777 vldrw.f32 q7, [q1, #4]
1778
1779 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1780 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1781 vldrw.32 q7, [q1, #4]
1782
1783 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1784 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1785 vldrw.s32 q7, [q1, #4]!
1786
1787 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1788 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1789 vldrw.f32 q7, [q1, #4]!
1790
1791 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1792 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1793 vldrw.u32 q7, [q1, #4]!
1794
1795 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1796 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1797 vstrw.u32 q0, [q1]
1798
1799 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1800 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1801 vstrw.s32 q0, [q1]
1802
1803 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1804 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1805 vstrw.f32 q0, [q1]
1806
1807 # CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
1808 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1809 vstrw.u32 q7, [q1]!
1810
1811 # CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
1812 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1813 vstrw.s32 q7, [q1]!
1814
1815 # CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
1816 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1817 vstrw.f32 q7, [q1]!
1818
1819 # CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
1820 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1821 vstrw.u32 q7, [q1, #508]
1822
1823 # CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
1824 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1825 vstrw.s32 q7, [q1, #508]
1826
1827 # CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
1828 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1829 vstrw.f32 q7, [q1, #508]
1830
1831 # CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1832 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1833 vstrw.u32 q7, [q1, #264]!
1834
1835 # CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1836 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1837 vstrw.s32 q7, [q1, #264]!
1838
1839 # CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1840 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1841 vstrw.f32 q7, [q1, #264]!
1842
1843 # CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
1844 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1845 vldrd.s64 q0, [q1]
1846
1847 # CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
1848 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1849 vldrd.f64 q0, [q1]
1850
1851 # CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
1852 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1853 vldrd.64 q0, [q1]
1854
1855 # CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
1856 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1857 vldrd.s64 q7, [q1]!
1858
1859 # CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
1860 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1861 vldrd.f64 q7, [q1]!
1862
1863 # CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
1864 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1865 vldrd.64 q7, [q1]!
1866
1867 # CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
1868 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1869 vldrd.s64 q7, [q1, #8]
1870
1871 # CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
1872 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1873 vldrd.f64 q7, [q1, #8]
1874
1875 # CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
1876 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1877 vldrd.64 q7, [q1, #8]
1878
1879 # CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
1880 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1881 vldrd.s64 q7, [q1, #-1016]!
1882
1883 # CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
1884 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1885 vldrd.f64 q7, [q1, #-1016]!
1886
1887 # CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
1888 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1889 vldrd.64 q7, [q1, #-1016]!
1890
1891 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
1892 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1893 vstrd.u64 q0, [q1]
1894
1895 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
1896 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1897 vstrd.s64 q0, [q1]
1898
1899 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
1900 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1901 vstrd.f64 q0, [q1]
1902
1903 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
1904 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1905 vstrd.u64 q7, [q1]!
1906
1907 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
1908 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1909 vstrd.s64 q7, [q1]!
1910
1911 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
1912 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1913 vstrd.f64 q7, [q1]!
1914
1915 # CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
1916 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1917 vstrd.u64 q7, [q1, #1016]
1918
1919 # CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
1920 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1921 vstrd.s64 q7, [q1, #1016]
1922
1923 # CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
1924 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1925 vstrd.f64 q7, [q1, #1016]
1926
1927 # CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
1928 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1929 vstrd.u64 q7, [q1, #-8]!
1930
1931 # CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
1932 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1933 vstrd.s64 q7, [q1, #-8]!
1934
1935 # CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
1936 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1937 vstrd.f64 q7, [q1, #-8]!
1938
1939 vpste
1940 vstrwt.f32 q7, [q1, #264]!
1941 vldrde.64 q7, [q1, #8]
1942 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
1943 # CHECK: vstrwt.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1944 # CHECK: vldrde.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]