test/MC/ARM/thumb-add-sub-width.s

   1 // RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
   2
   3   .text
   4   .thumb
   5
   6   // Check that the correct encoding of the add and sub instructions is
   7   // selected, for all combinations of flag-setting, condition and 2- or
   8   // 3-operand syntax.
   9
  10   .arch armv6-m
  11   add r0, r0, r1     // T2
  12   add r0, r1         // T2
  13   adds r0, r0, r1    // T1
  14   adds r0, r1        // T1
  15 // CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
  16 // CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
  17 // CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
  18 // CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
  19
  20   .arch armv7-m
  21   add r0, r0, r1     // T2, T3
  22   add r0, r1         // T2, T3
  23   adds r0, r0, r1    // T1, T3
  24   adds r0, r1        // T1, T3
  25 // CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
  26 // CHECK: add     r0, r1                  @ encoding: [0x08,0x44]
  27 // CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
  28 // CHECK: adds    r0, r0, r1              @ encoding: [0x40,0x18]
  29
  30   itttt eq
  31 // CHECK: itttt   eq                      @ encoding: [0x01,0xbf]
  32   addeq r0, r0, r1   // T1, T2, T3
  33   addeq r0, r1       // T2, T1, T3
  34   addseq r0, r0, r1  // T3
  35   addseq r0, r1      // T3
  36   // NOTE: Both T1 and T2 are valid for these two instructions, which one is
  37   // the preferred varies depending on whether the 2- or 3-operand syntax was
  38   // used.
  39 // CHECK: addeq   r0, r0, r1              @ encoding: [0x40,0x18]
  40 // CHECK: addeq   r0, r1                  @ encoding: [0x08,0x44]
  41 // CHECK: addseq.w        r0, r0, r1      @ encoding: [0x10,0xeb,0x01,0x00]
  42 // CHECK: addseq.w        r0, r0, r1      @ encoding: [0x10,0xeb,0x01,0x00]
  43
  44   .arch armv6-m
  45   // NOTE: There is no non-flag-setting sub instruction for v6-M
  46   subs r0, r0, r1    // T1, T2
  47   subs r0, r1        // T1, T2
  48 // CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
  49 // CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
  50
  51   .arch armv7-m
  52   sub r0, r0, r1     // T2
  53   sub r0, r1         // T2
  54   subs r0, r0, r1    // T1, T2
  55   subs r0, r1        // T1, T2
  56 // CHECK: sub.w   r0, r0, r1              @ encoding: [0xa0,0xeb,0x01,0x00]
  57 // CHECK: sub.w   r0, r0, r1              @ encoding: [0xa0,0xeb,0x01,0x00]
  58 // CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
  59 // CHECK: subs    r0, r0, r1              @ encoding: [0x40,0x1a]
  60
  61   itttt eq
  62 // CHECK: itttt   eq                      @ encoding: [0x01,0xbf]
  63   subeq r0, r0, r1   // T1, T2
  64   subeq r0, r1       // T1, T2
  65   subseq r0, r0, r1  // T2
  66   subseq r0, r1      // T2
  67 // CHECK: subeq   r0, r0, r1              @ encoding: [0x40,0x1a]
  68 // CHECK: subeq   r0, r0, r1              @ encoding: [0x40,0x1a]
  69 // CHECK: subseq.w        r0, r0, r1      @ encoding: [0xb0,0xeb,0x01,0x00]
  70 // CHECK: subseq.w        r0, r0, r1      @ encoding: [0xb0,0xeb,0x01,0x00]