test/MC/ARM/thumb-diagnostics.s

   1 @ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \
   2 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS %s
   3 @ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \
   4 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V5 %s
   5 @ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \
   6 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V7M %s
   7 @ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \
   8 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V8 %s
   9
  10 @ Check for various assembly diagnostic messages on invalid input.
  11
  12 @ ADD instruction w/o 'S' suffix.
  13         add r1, r2, r3
  14 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  15 @ CHECK-ERRORS:         add r1, r2, r3
  16 @ CHECK-ERRORS:         ^
  17 @ CHECK-ERRORS: note: instruction requires: arm-mode
  18 @ CHECK-ERRORS: note: instruction requires: thumb2
  19 @ CHECK-ERRORS: note: invalid operand for instruction
  20 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,7]
  21 @ CHECK-ERRORS: note: no flag-preserving variant of this instruction available
  22
  23 @ Instructions which require v6+ for both registers to be low regs.
  24         add r2, r3
  25         mov r2, r3
  26 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  27 @ CHECK-ERRORS:         add r2, r3
  28 @ CHECK-ERRORS:         ^
  29 @ CHECK-ERRORS: note: instruction variant requires Thumb2
  30 @ CHECK-ERRORS: note: operand must be a register sp
  31 @ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
  32 @ CHECK-ERRORS-V5:         mov r2, r3
  33 @ CHECK-ERRORS-V5:         ^
  34
  35 @ Immediates where registers were expected
  36         adds #0, r1, r2
  37         adds r0, #1, r2
  38 @ CHECK-ERRORS: error: operand must be a register in range [r0, r7]
  39 @ CHECK-ERRORS:         adds #0, r1, r2
  40 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  41 @ CHECK-ERRORS:         adds r0, #1, r2
  42 @ CHECK-ERRORS: note: operand must be a register in range [r0, r7]
  43 @ CHECK-ERRORS: note: too many operands for instruction
  44
  45 @ Out of range immediates for ASR instruction.
  46         asrs r2, r3, #33
  47 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  48 @ CHECK-ERRORS:         asrs r2, r3, #33
  49 @ CHECK-ERRORS:                      ^
  50 @ CHECK-ERRORS: note: operand must be an immediate in the range [1,32]
  51 @ CHECK-ERRORS: note: too many operands for instruction
  52
  53 @ Out of range immediates for BKPT instruction.
  54         bkpt #256
  55         bkpt #-1
  56 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  57 @ CHECK-ERRORS:        bkpt #256
  58 @ CHECK-ERRORS:             ^
  59 @ CHECK-ERRORS: note: instruction requires: arm-mode
  60 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]
  61 @ CHECK-ERRORS: note: too many operands for instruction
  62
  63 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
  64 @ CHECK-ERRORS:        bkpt #-1
  65 @ CHECK-ERRORS:             ^
  66 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]
  67 @ CHECK-ERRORS: note: too many operands for instruction
  68
  69 @ Out of range immediates for v8 HLT instruction.
  70         hlt #64
  71         hlt #-1
  72 @CHECK-ERRORS: error: invalid instruction
  73 @CHECK-ERRORS:        hlt #64
  74 @CHECK-ERRORS:        ^
  75 @CHECK-ERRORS-V8: error: invalid instruction, any one of the following would fix this:
  76 @CHECK-ERRORS-V8:         hlt #64
  77 @CHECK-ERRORS-V8:              ^
  78 @CHECK-ERRORS-V8: note: instruction requires: arm-mode
  79 @CHECK-ERRORS-V8: operand must be an immediate in the range [0,63]
  80 @CHECK-ERRORS: error: invalid instruction
  81 @CHECK-ERRORS:        hlt #-1
  82 @CHECK-ERRORS:        ^
  83 @CHECK-ERRORS-V8: error: operand must be an immediate in the range [0,63]
  84 @CHECK-ERRORS-V8:         hlt #-1
  85 @CHECK-ERRORS-V8:              ^
  86
  87 @ Invalid writeback and register lists for LDM
  88         ldm r2!, {r5, r8}
  89         ldm r2, {r5, r7}
  90         ldm r2!, {r2, r3, r4}
  91         ldm r2!, {r2, r3, r4, r10}
  92         ldmdb r2!, {r2, r3, r4}
  93         ldm r0, {r2, sp}
  94         ldmia r0, {r2-r3, sp}
  95         ldmia r0!, {r2-r3, sp}
  96         ldmfd r2, {r1, r3-r6, sp}
  97         ldmfd r2!, {r1, r3-r6, sp}
  98         ldmdb r1, {r2, r3, sp}
  99         ldmdb r1!, {r2, r3, sp}
 100 @ CHECK-ERRORS: error: registers must be in range r0-r7
 101 @ CHECK-ERRORS:         ldm r2!, {r5, r8}
 102 @ CHECK-ERRORS:                  ^
 103 @ CHECK-ERRORS: error: writeback operator '!' expected
 104 @ CHECK-ERRORS:         ldm r2, {r5, r7}
 105 @ CHECK-ERRORS:             ^
 106 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
 107 @ CHECK-ERRORS:         ldm r2!, {r2, r3, r4}
 108 @ CHECK-ERRORS:               ^
 109 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
 110 @ CHECK-ERRORS-V8:         ldm r2!, {r2, r3, r4, r10}
 111 @ CHECK-ERRORS-V8:               ^
 112 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
 113 @ CHECK-ERRORS-V8:         ldmdb r2!, {r2, r3, r4}
 114 @ CHECK-ERRORS-V8:                 ^
 115 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 116 @ CHECK-ERRORS-V7M:         ldm r0, {r2, sp}
 117 @ CHECK-ERRORS-V7M:                 ^
 118 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 119 @ CHECK-ERRORS-V7M:         ldmia r0, {r2-r3, sp}
 120 @ CHECK-ERRORS-V7M:                   ^
 121 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 122 @ CHECK-ERRORS-V7M:         ldmia r0!, {r2-r3, sp}
 123 @ CHECK-ERRORS-V7M:                    ^
 124 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 125 @ CHECK-ERRORS-V7M:         ldmfd r2, {r1, r3-r6, sp}
 126 @ CHECK-ERRORS-V7M:                   ^
 127 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 128 @ CHECK-ERRORS-V7M:         ldmfd r2!, {r1, r3-r6, sp}
 129 @ CHECK-ERRORS-V7M:                    ^
 130 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 131 @ CHECK-ERRORS-V7M:         ldmdb r1, {r2, r3, sp}
 132 @ CHECK-ERRORS-V7M:                   ^
 133 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 134 @ CHECK-ERRORS-V7M:         ldmdb r1!, {r2, r3, sp}
 135 @ CHECK-ERRORS-V7M:                    ^
 136
 137 @ Invalid writeback and register lists for PUSH/POP
 138         pop {r1, r2, r10}
 139         push {r8, r9}
 140 @ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
 141 @ CHECK-ERRORS:         pop {r1, r2, r10}
 142 @ CHECK-ERRORS:             ^
 143 @ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
 144 @ CHECK-ERRORS:         push {r8, r9}
 145 @ CHECK-ERRORS:              ^
 146
 147
 148 @ Invalid writeback and register lists for STM
 149         stm r1, {r2, r6}
 150         stm r1!, {r2, r9}
 151         stm r2!, {r2, r9}
 152         stmdb r2!, {r0, r2}
 153         stm r1!, {r2, sp}
 154         stmia r4!, {r0-r3, sp}
 155         stmdb r1, {r2, r3, sp}
 156         stmdb r1!, {r2, r3, sp}
 157 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 158 @ CHECK-ERRORS:         stm r1, {r2, r6}
 159 @ CHECK-ERRORS:         ^
 160 @ CHECK-ERRORS: note: instruction requires: thumb2
 161 @ CHECK-ERRORS: note: instruction requires: arm-mode
 162 @ CHECK-ERRORS: error: registers must be in range r0-r7
 163 @ CHECK-ERRORS:         stm r1!, {r2, r9}
 164 @ CHECK-ERRORS:                  ^
 165 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
 166 @ CHECK-ERRORS-V8:         stm r2!, {r2, r9}
 167 @ CHECK-ERRORS-V8:                  ^
 168 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
 169 @ CHECK-ERRORS-V8:         stmdb r2!, {r0, r2}
 170 @ CHECK-ERRORS-V8:                  ^
 171 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 172 @ CHECK-ERRORS-V7M:         stm r1!, {r2, sp}
 173 @ CHECK-ERRORS-V7M:                  ^
 174 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 175 @ CHECK-ERRORS-V7M:         stmia r4!, {r0-r3, sp}
 176 @ CHECK-ERRORS-V7M:                    ^
 177 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 178 @ CHECK-ERRORS-V7M:         stmdb r1, {r2, r3, sp}
 179 @ CHECK-ERRORS-V7M:                   ^
 180 @ CHECK-ERRORS-V7M: error: SP may not be in the register list
 181 @ CHECK-ERRORS-V7M:         stmdb r1!, {r2, r3, sp}
 182 @ CHECK-ERRORS-V7M:                    ^
 183
 184 @ Out of range immediates for LSL instruction.
 185         lsls r4, r5, #-1
 186         lsls r4, r5, #32
 187 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 188 @ CHECK-ERRORS:         lsls r4, r5, #-1
 189 @ CHECK-ERRORS:                      ^
 190 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 191 @ CHECK-ERRORS: note: too many operands for instruction
 192 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 193 @ CHECK-ERRORS:         lsls r4, r5, #32
 194 @ CHECK-ERRORS:                      ^
 195 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,31]
 196 @ CHECK-ERRORS: note: too many operands for instruction
 197
 198 @ Mismatched source/destination operands for MUL instruction.
 199         muls r1, r2, r3
 200 @ CHECK-ERRORS: error: destination register must match source register
 201 @ CHECK-ERRORS:         muls r1, r2, r3
 202 @ CHECK-ERRORS:              ^
 203
 204
 205 @ Out of range immediates for STR instruction.
 206         str r2, [r7, #-1]
 207         str r5, [r1, #3]
 208         str r3, [r7, #128]
 209 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 210 @ CHECK-ERRORS:         str r2, [r7, #-1]
 211 @ CHECK-ERRORS:         ^
 212 @ CHECK-ERRORS: note: instruction requires: thumb2
 213 @ CHECK-ERRORS: note: instruction requires: arm-mode
 214 @ CHECK-ERRORS: note: invalid operand for instruction
 215 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 216 @ CHECK-ERRORS:         str r5, [r1, #3]
 217 @ CHECK-ERRORS:         ^
 218 @ CHECK-ERRORS: note: instruction requires: thumb2
 219 @ CHECK-ERRORS: note: instruction requires: arm-mode
 220 @ CHECK-ERRORS: note: invalid operand for instruction
 221 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 222 @ CHECK-ERRORS:         str r3, [r7, #128]
 223 @ CHECK-ERRORS:         ^
 224 @ CHECK-ERRORS: note: instruction requires: thumb2
 225 @ CHECK-ERRORS: note: instruction requires: arm-mode
 226 @ CHECK-ERRORS: note: invalid operand for instruction
 227
 228 @ Out of range immediate for SVC instruction.
 229         svc #-1
 230         svc #256
 231 @ CHECK-ERRORS: error: operand must be an immediate in the range [0,255]
 232 @ CHECK-ERRORS:         svc #-1
 233 @ CHECK-ERRORS:             ^
 234 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 235 @ CHECK-ERRORS:         svc #256
 236 @ CHECK-ERRORS:         ^
 237 @ CHECK-ERRORS: note: instruction requires: arm-mode
 238 @ CHECK-ERRORS: note: operand must be an immediate in the range [0,255]
 239
 240
 241 @ Out of range immediate for ADD SP instructions
 242         add sp, #-1
 243         add sp, #3
 244         add sp, sp, #512
 245         add r2, sp, #1024
 246 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 247 @ CHECK-ERRORS:         add sp, #-1
 248 @ CHECK-ERRORS:                 ^
 249 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
 250 @ CHECK-ERRORS: note: instruction requires: thumb2
 251 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 252 @ CHECK-ERRORS:         add sp, #3
 253 @ CHECK-ERRORS:                 ^
 254 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
 255 @ CHECK-ERRORS: note: instruction requires: thumb2
 256 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 257 @ CHECK-ERRORS:         add sp, sp, #512
 258 @ CHECK-ERRORS:                     ^
 259 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
 260 @ CHECK-ERRORS: note: instruction requires: thumb2
 261 @ CHECK-ERRORS: error: instruction requires: thumb2
 262 @ CHECK-ERRORS:         add r2, sp, #1024
 263 @ CHECK-ERRORS:         ^
 264
 265         add r2, sp, ip
 266 @ CHECK-ERRORS: error: source register must be the same as destination
 267 @ CHECK-ERRORS:         add r2, sp, ip
 268 @ CHECK-ERRORS:                     ^
 269
 270
 271 @------------------------------------------------------------------------------
 272 @ B/Bcc - out of range immediates for Thumb1 branches
 273 @------------------------------------------------------------------------------
 274
 275         beq    #-258
 276         bne    #256
 277         bgt    #13
 278         b      #-1048578
 279         b      #1048576
 280         b      #10323
 281
 282 @ CHECK-ERRORS: error: branch target out of range
 283 @ CHECK-ERRORS: error: branch target out of range
 284 @ CHECK-ERRORS: error: branch target out of range
 285 @ CHECK-ERRORS: error: branch target out of range
 286 @ CHECK-ERRORS: error: branch target out of range
 287 @ CHECK-ERRORS: error: branch target out of range
 288
 289 @------------------------------------------------------------------------------
 290 @ CBZ/CBNZ - out of range immediates for branches
 291 @------------------------------------------------------------------------------
 292
 293         cbz    r0, #-2
 294         cbz    r0, #0
 295         cbz    r0, #17
 296         cbnz   r0, #126
 297         cbnz   r0, #128
 298
 299 @ CHECK-ERRORS-V7M: error: branch target out of range
 300 @ CHECK-ERRORS-V7M: error: invalid operand for instruction
 301 @ CHECK-ERRORS-V7M: error: branch target out of range
 302 @ CHECK-ERRORS-V8: error: branch target out of range
 303 @ CHECK-ERRORS-V8: error: invalid operand for instruction
 304 @ CHECK-ERRORS-V8: error: branch target out of range
 305
 306 @------------------------------------------------------------------------------
 307 @ SEV/WFE/WFI/YIELD - are not supported pre v6M or v6T2
 308 @------------------------------------------------------------------------------
 309         sev
 310         wfe
 311         wfi
 312         yield
 313
 314 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 315 @ CHECK-ERRORS: sev
 316 @ CHECK-ERRORS: ^
 317 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 318 @ CHECK-ERRORS: wfe
 319 @ CHECK-ERRORS: ^
 320 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 321 @ CHECK-ERRORS: wfi
 322 @ CHECK-ERRORS: ^
 323 @ CHECK-ERRORS: error: instruction requires: armv6m or armv6t2
 324 @ CHECK-ERRORS: yield
 325 @ CHECK-ERRORS: ^
 326
 327 @------------------------------------------------------------------------------
 328 @ PLDW required mp-extensions
 329 @------------------------------------------------------------------------------
 330         pldw [r0, #4]
 331 @ CHECK-ERRORS: error: instruction requires: mp-extensions
 332
 333 @------------------------------------------------------------------------------
 334 @ LDR(lit) - invalid offsets
 335 @------------------------------------------------------------------------------
 336
 337         ldr r4, [pc, #-12]
 338 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 339 @ CHECK-ERRORS: note: instruction requires: thumb2
 340 @ CHECK-ERRORS: note: instruction requires: arm-mode
 341 @ CHECK-ERRORS: note: invalid operand for instruction
 342
 343 @------------------------------------------------------------------------------
 344 @ STC2{L}/LDC2{L} - requires thumb2
 345 @------------------------------------------------------------------------------
 346         stc2 p0, c8, [r1, #4]
 347         stc2l p6, c2, [r7, #4]
 348         ldc2 p0, c8, [r1, #4]
 349         ldc2l p6, c2, [r7, #4]
 350 @ CHECK-ERRORS: error: invalid instruction
 351 @ CHECK-ERRORS: error: invalid instruction
 352 @ CHECK-ERRORS: error: invalid instruction
 353 @ CHECK-ERRORS: error: invalid instruction
 354
 355 @------------------------------------------------------------------------------
 356 @ Generic error for too few operands
 357 @------------------------------------------------------------------------------
 358
 359         adds
 360         adds r0
 361 @ CHECK-ERRORS: error: too few operands for instruction
 362 @ CHECK-ERRORS: error: too few operands for instruction
 363
 364 @------------------------------------------------------------------------------
 365 @ Out of range width for SBFX/UBFX
 366 @------------------------------------------------------------------------------
 367
 368         sbfx r4, r5, #31, #2
 369         ubfx r4, r5, #16, #17
 370
 371 @ CHECK-ERRORS-V8: error: bitfield width must be in range [1,32-lsb]
 372 @ CHECK-ERRORS-V8:         sbfx r4, r5, #31, #2
 373 @ CHECK-ERRORS-V8:                           ^
 374 @ CHECK-ERRORS-V8: error: bitfield width must be in range [1,32-lsb]
 375 @ CHECK-ERRORS-V8:         ubfx r4, r5, #16, #17
 376 @ CHECK-ERRORS-V8:                           ^
 377
 378 @------------------------------------------------------------------------------
 379 @ Writeback store writing to same register as value
 380 @------------------------------------------------------------------------------
 381
 382         str r0, [r0, #4]!
 383         str r0, [r0], #4
 384         strh r0, [r0, #2]!
 385         strh r0, [r0], #2
 386         strb r0, [r0, #1]!
 387         strb r0, [r0], #1
 388         strd r0, r1, [r0], #1
 389         strd r1, r0, [r0], #1
 390 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 391 @ CHECK-ERRORS-V8: str r0, [r0, #4]!
 392 @ CHECK-ERRORS-V8:         ^
 393 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 394 @ CHECK-ERRORS-V8: str r0, [r0], #4
 395 @ CHECK-ERRORS-V8:         ^
 396 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 397 @ CHECK-ERRORS-V8: strh r0, [r0, #2]!
 398 @ CHECK-ERRORS-V8:          ^
 399 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 400 @ CHECK-ERRORS-V8: strh r0, [r0], #2
 401 @ CHECK-ERRORS-V8:          ^
 402 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 403 @ CHECK-ERRORS-V8: strb r0, [r0, #1]!
 404 @ CHECK-ERRORS-V8:          ^
 405 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 406 @ CHECK-ERRORS-V8: strb r0, [r0], #1
 407 @ CHECK-ERRORS-V8:          ^
 408 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 409 @ CHECK-ERRORS-V8: strd r0, r1, [r0], #1
 410 @ CHECK-ERRORS-V8:              ^
 411 @ CHECK-ERRORS-V8: error: source register and base register can't be identical
 412 @ CHECK-ERRORS-V8: strd r1, r0, [r0], #1
 413 @ CHECK-ERRORS-V8:              ^