test/MC/ARM/vscclrm-asm.s

   1 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding < %s 2>%t \
   2 // RUN: | FileCheck --check-prefix=CHECK %s
   3 // RUN:   FileCheck --check-prefix=ERROR < %t %s
   4 // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \
   5 // RUN: | FileCheck --check-prefix=CHECK %s
   6 // RUN:   FileCheck --check-prefix=ERROR < %t %s
   7 // RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t
   8 // RUN: FileCheck --check-prefix=NOSEC < %t %s
   9
  10 // CHECK: vscclrm            {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]
  11 // NOSEC: instruction requires: ARMv8-M Security Extensions
  12 vscclrm {s0-s3, vpr}
  13
  14 // CHECK: vscclrm            {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
  15 // NOSEC: instruction requires: ARMv8-M Security Extensions
  16 vscclrm {s3-s8, vpr}
  17
  18 // CHECK: vscclrm            {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} @ encoding: [0x9f,0xec,0x0c,0x9a]
  19 vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
  20
  21 // CHECK: vscclrm            {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]
  22 vscclrm {s31, vpr}
  23
  24 // CHECK: vscclrm            {d0, d1, vpr}  @ encoding: [0x9f,0xec,0x04,0x0b]
  25 vscclrm {d0-d1, vpr}
  26
  27 // CHECK: vscclrm            {d0, d1, d2, d3, vpr}  @ encoding: [0x9f,0xec,0x08,0x0b]
  28 vscclrm {d0-d3, vpr}
  29
  30 // CHECK: vscclrm            {d5, d6, d7, vpr}  @ encoding: [0x9f,0xec,0x06,0x5b]
  31 vscclrm {d5-d7, vpr}
  32
  33 // CHECK: it                 hi @ encoding: [0x88,0xbf]
  34 it hi
  35 // CHECK: vscclrmhi          {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} @ encoding: [0xdf,0xec,0x1d,0x1a]
  36 vscclrmhi {s3-s31, vpr}
  37
  38 // ERROR: non-contiguous register range
  39 vscclrm {s0, s3-s4, vpr}
  40
  41 // ERROR: register expected
  42 vscclrm {s32, vpr}
  43
  44 // ERROR: invalid operand for instruction
  45 vscclrm {s0-s1}