test/MC/Lanai/memory.s

   1 ! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
   2
   3 ! Checking the machine instructions generated from ASM instructions for ALU
   4 ! operations.
   5
   6 ! RM class
   7     ld [%r7], %r6
   8 ! CHECK: encoding: [0x83,0x1c,0x00,0x00]
   9 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  10 ! CHECK-NEXT: <MCOperand Reg:13>
  11 ! CHECK-NEXT: <MCOperand Reg:14>
  12 ! CHECK-NEXT: <MCOperand Imm:0>
  13 ! CHECK-NEXT: <MCOperand Imm:0>
  14
  15     ld [%r6], %r6
  16 ! CHECK: encoding: [0x83,0x18,0x00,0x00]
  17 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  18 ! CHECK-NEXT: <MCOperand Reg:13>
  19 ! CHECK-NEXT: <MCOperand Reg:13>
  20 ! CHECK-NEXT: <MCOperand Imm:0>
  21 ! CHECK-NEXT: <MCOperand Imm:0>
  22
  23      st %r6, [%r7]
  24 ! CHECK: encoding: [0x93,0x1c,0x00,0x00]
  25 ! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
  26 ! CHECK-NEXT: <MCOperand Reg:13>
  27 ! CHECK-NEXT: <MCOperand Reg:14>
  28 ! CHECK-NEXT: <MCOperand Imm:0>
  29 ! CHECK-NEXT: <MCOperand Imm:0>
  30
  31     ld 0x123[%r7*], %r6
  32 ! CHECK: encoding: [0x83,0x1d,0x01,0x23]
  33 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  34 ! CHECK-NEXT: <MCOperand Reg:13>
  35 ! CHECK-NEXT: <MCOperand Reg:14>
  36 ! CHECK-NEXT: <MCOperand Imm:291>
  37 ! CHECK-NEXT: <MCOperand Imm:128>
  38
  39     ld [%r7--], %r6
  40 ! CHECK: encoding: [0x83,0x1d,0xff,0xfc]
  41 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  42 ! CHECK-NEXT: <MCOperand Reg:13>
  43 ! CHECK-NEXT: <MCOperand Reg:14>
  44 ! CHECK-NEXT: <MCOperand Imm:-4>
  45 ! CHECK-NEXT: <MCOperand Imm:128>
  46
  47     ld 0x123[%r7], %r6
  48 ! CHECK: encoding: [0x83,0x1e,0x01,0x23]
  49 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  50 ! CHECK-NEXT: <MCOperand Reg:13>
  51 ! CHECK-NEXT: <MCOperand Reg:14>
  52 ! CHECK-NEXT: <MCOperand Imm:291>
  53 ! CHECK-NEXT: <MCOperand Imm:0>
  54
  55     ld 0x123[*%r7], %r6
  56 ! CHECK: encoding: [0x83,0x1f,0x01,0x23]
  57 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  58 ! CHECK-NEXT: <MCOperand Reg:13>
  59 ! CHECK-NEXT: <MCOperand Reg:14>
  60 ! CHECK-NEXT: <MCOperand Imm:291>
  61 ! CHECK-NEXT: <MCOperand Imm:64>
  62
  63     ld [--%r7], %r6
  64 ! CHECK: encoding: [0x83,0x1f,0xff,0xfc]
  65 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  66 ! CHECK-NEXT: <MCOperand Reg:13>
  67 ! CHECK-NEXT: <MCOperand Reg:14>
  68 ! CHECK-NEXT: <MCOperand Imm:-4>
  69 ! CHECK-NEXT: <MCOperand Imm:64>
  70
  71     st %r6, [%r7++]
  72 ! CHECK: encoding: [0x93,0x1d,0x00,0x04]
  73 ! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
  74 ! CHECK-NEXT: <MCOperand Reg:13>
  75 ! CHECK-NEXT: <MCOperand Reg:14>
  76 ! CHECK-NEXT: <MCOperand Imm:4>
  77 ! CHECK-NEXT: <MCOperand Imm:128>
  78
  79     st.h %r6, [%r7++]
  80 ! CHECK: encoding: [0xf3,0x1f,0x24,0x02]
  81 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STH_RI{{$}}
  82 ! CHECK-NEXT: <MCOperand Reg:13>
  83 ! CHECK-NEXT: <MCOperand Reg:14>
  84 ! CHECK-NEXT: <MCOperand Imm:2>
  85 ! CHECK-NEXT: <MCOperand Imm:128>>
  86
  87     ld.b [--%r7], %r6
  88 ! CHECK: encoding: [0xf3,0x1f,0x4f,0xff]
  89 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RI{{$}}
  90 ! CHECK-NEXT: <MCOperand Reg:13>
  91 ! CHECK-NEXT: <MCOperand Reg:14>
  92 ! CHECK-NEXT: <MCOperand Imm:-1>
  93 ! CHECK-NEXT: <MCOperand Imm:64>>
  94
  95 ! Largest RM value before SLS encoding is used
  96     ld [0x7fff], %r7
  97 ! CHECK: encoding: [0x83,0x82,0x7f,0xff]
  98 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
  99 ! CHECK-NEXT: <MCOperand Reg:14>
 100 ! CHECK-NEXT: <MCOperand Reg:7>
 101 ! CHECK-NEXT: <MCOperand Imm:32767>
 102 ! CHECK-NEXT: <MCOperand Imm:0>
 103
 104     ld [0x8000], %r7
 105 ! CHECK: encoding: [0xf3,0x80,0x80,0x00]
 106 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
 107 ! CHECK-NEXT: <MCOperand Reg:14>
 108 ! CHECK-NEXT: <MCOperand Imm:32768>
 109
 110 ! Negative RM value
 111     ld [0xfffffe8c], %pc
 112 ! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
 113 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
 114 ! CHECK-NEXT: <MCOperand Reg:2>
 115 ! CHECK-NEXT: <MCOperand Reg:7>
 116 ! CHECK-NEXT: <MCOperand Imm:-372>
 117 ! CHECK-NEXT: <MCOperand Imm:0>
 118
 119     ld [-372], %pc
 120 ! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
 121 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
 122 ! CHECK-NEXT: <MCOperand Reg:2>
 123 ! CHECK-NEXT: <MCOperand Reg:7>
 124 ! CHECK-NEXT: <MCOperand Imm:-372>
 125 ! CHECK-NEXT: <MCOperand Imm:0>
 126
 127 ! RRM class
 128     ld %r9[%r12*], %r20
 129 ! CHECK: encoding: [0xaa,0x31,0x48,0x02]
 130 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
 131 ! CHECK-NEXT: <MCOperand Reg:27>
 132 ! CHECK-NEXT: <MCOperand Reg:19>
 133 ! CHECK-NEXT: <MCOperand Reg:16>
 134 ! CHECK-NEXT: <MCOperand Imm:128>
 135
 136     ld %r9[%r12], %r20
 137 ! CHECK: encoding: [0xaa,0x32,0x48,0x02]
 138 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
 139 ! CHECK-NEXT: <MCOperand Reg:27>
 140 ! CHECK-NEXT: <MCOperand Reg:19>
 141 ! CHECK-NEXT: <MCOperand Reg:16>
 142 ! CHECK-NEXT: <MCOperand Imm:0>
 143
 144     ld [%r12 sub %r9], %r20
 145 ! CHECK: encoding: [0xaa,0x32,0x4a,0x02]
 146 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
 147 ! CHECK-NEXT: <MCOperand Reg:27>
 148 ! CHECK-NEXT: <MCOperand Reg:19>
 149 ! CHECK-NEXT: <MCOperand Reg:16>
 150 ! CHECK-NEXT: <MCOperand Imm:2>
 151
 152     ld %r9[*%r12], %r20
 153 ! CHECK: encoding: [0xaa,0x33,0x48,0x02]
 154 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
 155 ! CHECK-NEXT: <MCOperand Reg:27>
 156 ! CHECK-NEXT: <MCOperand Reg:19>
 157 ! CHECK-NEXT: <MCOperand Reg:16>
 158 ! CHECK-NEXT: <MCOperand Imm:64>
 159
 160     st %r20, %r9[*%r12]
 161 ! CHECK: encoding: [0xba,0x33,0x48,0x02]
 162 ! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RR{{$}}
 163 ! CHECK-NEXT: <MCOperand Reg:27>
 164 ! CHECK-NEXT: <MCOperand Reg:19>
 165 ! CHECK-NEXT: <MCOperand Reg:16>
 166 ! CHECK-NEXT: <MCOperand Imm:64>
 167
 168     ld.b [%r12 sub %r9], %r20
 169 ! CHECK: encoding: [0xaa,0x32,0x4a,0x04]
 170 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RR{{$}}
 171 ! CHECK-NEXT: <MCOperand Reg:27>
 172 ! CHECK-NEXT: <MCOperand Reg:19>
 173 ! CHECK-NEXT: <MCOperand Reg:16>
 174 ! CHECK-NEXT: <MCOperand Imm:2>
 175
 176     uld.h [%r12 sub %r9], %r20
 177 ! CHECK: encoding: [0xaa,0x32,0x4a,0x01]
 178 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDHz_RR{{$}}
 179 ! CHECK-NEXT: <MCOperand Reg:27>
 180 ! CHECK-NEXT: <MCOperand Reg:19>
 181 ! CHECK-NEXT: <MCOperand Reg:16>
 182 ! CHECK-NEXT: <MCOperand Imm:2>
 183
 184
 185 ! SPLS class
 186     st.b %r3, [%r6]
 187 ! CHECK: encoding: [0xf1,0x9b,0x60,0x00]
 188 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
 189 ! CHECK-NEXT: <MCOperand Reg:10>
 190 ! CHECK-NEXT: <MCOperand Reg:13>
 191 ! CHECK-NEXT: <MCOperand Imm:0>
 192 ! CHECK-NEXT: <MCOperand Imm:0>
 193
 194     st.b %r3, 1[%r6*]
 195 ! CHECK: encoding: [0xf1,0x9b,0x64,0x01]
 196 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
 197 ! CHECK-NEXT: <MCOperand Reg:10>
 198 ! CHECK-NEXT: <MCOperand Reg:13>
 199 ! CHECK-NEXT: <MCOperand Imm:1>
 200 ! CHECK-NEXT: <MCOperand Imm:128>
 201
 202     st.b %r3, 1[%r6]
 203 ! CHECK: encoding: [0xf1,0x9b,0x68,0x01]
 204 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
 205 ! CHECK-NEXT: <MCOperand Reg:10>
 206 ! CHECK-NEXT: <MCOperand Reg:13>
 207 ! CHECK-NEXT: <MCOperand Imm:1>
 208 ! CHECK-NEXT: <MCOperand Imm:0>
 209
 210     st.b %r3, 1[*%r6]
 211 ! CHECK: encoding: [0xf1,0x9b,0x6c,0x01]
 212 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
 213 ! CHECK-NEXT: <MCOperand Reg:10>
 214 ! CHECK-NEXT: <MCOperand Reg:13>
 215 ! CHECK-NEXT: <MCOperand Imm:1>
 216 ! CHECK-NEXT: <MCOperand Imm:64>
 217
 218 ! SLS class
 219     st %r30, [0x1234]
 220 ! CHECK: encoding: [0xff,0x01,0x12,0x34]
 221 ! CHECK-NEXT: <MCInst #{{[0-9]+}} STADDR{{$}}
 222 ! CHECK-NEXT: <MCOperand Reg:37>
 223 ! CHECK-NEXT: <MCOperand Imm:4660>
 224
 225     ld [0xfe8c], %pc
 226 ! CHECK: encoding: [0xf1,0x00,0xfe,0x8c]
 227 ! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
 228 ! CHECK-NEXT: <MCOperand Reg:2>
 229 ! CHECK-NEXT: <MCOperand Imm:65164>
 230
 231 ! SLI class
 232     mov hi(x), %r4
 233 ! CHECK: encoding: [0x02,0x01,A,A]
 234 ! CHECK-NEXT: fixup A - offset: 0, value: hi(x), kind: FIXUP_LANAI_HI16{{$}}
 235 ! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
 236 ! CHECK-NEXT: <MCOperand Reg:11>
 237 ! CHECK-NEXT: <MCOperand Reg:7>
 238 ! CHECK-NEXT: <MCOperand Expr:(hi(x))>
 239
 240     mov hi(l+4), %r7
 241 ! CHECK: encoding: [0x03,0x81,A,A]
 242 ! CHECK-NEXT: fixup A - offset: 0, value: (hi(l))+4, kind: FIXUP_LANAI_HI16{{$}}
 243 ! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
 244 ! CHECK-NEXT: <MCOperand Reg:14>
 245 ! CHECK-NEXT: <MCOperand Reg:7>
 246 ! CHECK-NEXT: <MCOperand Expr:((hi(l))+4)>
 247