lib/Target/IA64/IA64Bundling.cpp

   1 //===-- IA64Bundling.cpp - IA-64 instruction bundling pass. ------------ --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Duraid Madina and is distributed under the
   6 // University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Add stops where required to prevent read-after-write and write-after-write
  11 // dependencies, for both registers and memory addresses. There are exceptions:
  12 //
  13 //    - Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
  14 //      WAW dependencies so long as they all target p0, or are of parallel
  15 //      type (.and*/.or*)
  16 //
  17 // FIXME: bundling, for now, is left to the assembler.
  18 // FIXME: this might be an appropriate place to translate between different
  19 //        instructions that do the same thing, if this helps bundling.
  20 //
  21 //===----------------------------------------------------------------------===//
  22
  23 #include "IA64.h"
  24 #include "llvm/CodeGen/MachineFunctionPass.h"
  25 #include "llvm/CodeGen/MachineInstrBuilder.h"
  26 #include "llvm/ADT/SetOperations.h"
  27 #include "llvm/ADT/Statistic.h"
  28 #include "llvm/Support/Debug.h"
  29 #include <set>
  30 #include <iostream>
  31 using namespace llvm;
  32
  33 namespace {
  34   Statistic<> StopBitsAdded("ia64-codegen", "Number of stop bits added");
  35
  36   struct IA64BundlingPass : public MachineFunctionPass {
  37     /// Target machine description which we query for reg. names, data
  38     /// layout, etc.
  39     ///
  40     IA64TargetMachine &TM;
  41
  42     IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }
  43
  44     virtual const char *getPassName() const {
  45       return "IA64 (Itanium) Bundling Pass";
  46     }
  47
  48     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
  49     bool runOnMachineFunction(MachineFunction &F) {
  50       bool Changed = false;
  51       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
  52            FI != FE; ++FI)
  53         Changed |= runOnMachineBasicBlock(*FI);
  54       return Changed;
  55     }
  56
  57     std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
  58                          // pending writes can cross basic blocks. Note that
  59                          // taken branches end instruction groups. So we
  60                          // only need to worry about 'fallthrough' code
  61   };
  62 } // end of anonymous namespace
  63
  64 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
  65 /// and arranges the result into bundles.
  66 ///
  67 FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
  68   return new IA64BundlingPass(tm);
  69 }
  70
  71 /// runOnMachineBasicBlock - add stops and bundle this MBB.
  72 ///
  73 bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
  74   bool Changed = false;
  75
  76   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
  77     MachineInstr *CurrentInsn = I++;
  78     std::set<unsigned> CurrentReads, CurrentWrites, OrigWrites;
  79
  80     for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
  81       MachineOperand &MO=CurrentInsn->getOperand(i);
  82       if(MO.isRegister()) {
  83         if(MO.isUse()) { // TODO: exclude p0
  84           CurrentReads.insert(MO.getReg());
  85         }
  86         if(MO.isDef()) { // TODO: exclude p0
  87           CurrentWrites.insert(MO.getReg());
  88           OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
  89                                           // set_intersect instead?
  90         }
  91       }
  92     }
  93
  94     // CurrentReads/CurrentWrites contain info for the current instruction.
  95     // Does it read or write any registers that are pending a write?
  96     // (i.e. not separated by a stop)
  97     set_intersect(CurrentReads, PendingRegWrites);
  98     set_intersect(CurrentWrites, PendingRegWrites);
  99
 100     if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
 101       // there is a conflict, insert a stop and reset PendingRegWrites
 102       CurrentInsn = BuildMI(MBB, CurrentInsn, IA64::STOP, 0);
 103       PendingRegWrites=OrigWrites; // carry over current writes to next insn
 104       Changed=true; StopBitsAdded++; // update stats
 105     } else { // otherwise, track additional pending writes
 106       set_union(PendingRegWrites, OrigWrites);
 107     }
 108   } // onto the next insn in the MBB
 109
 110   return Changed;
 111 }
 112