lib/Target/IA64/IA64ISelDAGToDAG.cpp

   1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Duraid Madina and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for IA64,
  11 // converting a legalized dag to an IA64 dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "IA64.h"
  16 #include "IA64TargetMachine.h"
  17 #include "IA64ISelLowering.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/SSARegMap.h"
  21 #include "llvm/CodeGen/SelectionDAG.h"
  22 #include "llvm/CodeGen/SelectionDAGISel.h"
  23 #include "llvm/Target/TargetOptions.h"
  24 #include "llvm/ADT/Statistic.h"
  25 #include "llvm/Constants.h"
  26 #include "llvm/GlobalValue.h"
  27 #include "llvm/Intrinsics.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MathExtras.h"
  30 #include <iostream>
  31 #include <set>
  32 using namespace llvm;
  33
  34 namespace {
  35   Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
  36   Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
  37
  38   //===--------------------------------------------------------------------===//
  39   /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
  40   /// instructions for SelectionDAG operations.
  41   ///
  42   class IA64DAGToDAGISel : public SelectionDAGISel {
  43     IA64TargetLowering IA64Lowering;
  44     unsigned GlobalBaseReg;
  45   public:
  46     IA64DAGToDAGISel(IA64TargetMachine &TM)
  47       : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
  48
  49     virtual bool runOnFunction(Function &Fn) {
  50       // Make sure we re-emit a set of the global base reg if necessary
  51       GlobalBaseReg = 0;
  52       return SelectionDAGISel::runOnFunction(Fn);
  53     }
  54
  55     /// getI64Imm - Return a target constant with the specified value, of type
  56     /// i64.
  57     inline SDOperand getI64Imm(uint64_t Imm) {
  58       return CurDAG->getTargetConstant(Imm, MVT::i64);
  59     }
  60
  61     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
  62     /// base register.  Return the virtual register that holds this value.
  63     // SDOperand getGlobalBaseReg(); TODO: hmm
  64
  65     // Select - Convert the specified operand from a target-independent to a
  66     // target-specific node if it hasn't already been changed.
  67     void Select(SDOperand &Result, SDOperand N);
  68
  69     SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
  70                                    unsigned OCHi, unsigned OCLo,
  71                                    bool IsArithmetic = false,
  72                                    bool Negate = false);
  73     SDNode *SelectBitfieldInsert(SDNode *N);
  74
  75     /// SelectCC - Select a comparison of the specified values with the
  76     /// specified condition code, returning the CR# of the expression.
  77     SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
  78
  79     /// SelectAddr - Given the specified address, return the two operands for a
  80     /// load/store instruction, and return true if it should be an indexed [r+r]
  81     /// operation.
  82     bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
  83
  84     SDOperand BuildSDIVSequence(SDNode *N);
  85     SDOperand BuildUDIVSequence(SDNode *N);
  86
  87     /// InstructionSelectBasicBlock - This callback is invoked by
  88     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
  89     virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
  90
  91     virtual const char *getPassName() const {
  92       return "IA64 (Itanium) DAG->DAG Instruction Selector";
  93     }
  94
  95 // Include the pieces autogenerated from the target description.
  96 #include "IA64GenDAGISel.inc"
  97
  98 private:
  99     SDOperand SelectDIV(SDOperand Op);
 100   };
 101 }
 102
 103 /// InstructionSelectBasicBlock - This callback is invoked by
 104 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 105 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 106   DEBUG(BB->dump());
 107
 108   // The selection process is inherently a bottom-up recursive process (users
 109   // select their uses before themselves).  Given infinite stack space, we
 110   // could just start selecting on the root and traverse the whole graph.  In
 111   // practice however, this causes us to run out of stack space on large basic
 112   // blocks.  To avoid this problem, select the entry node, then all its uses,
 113   // iteratively instead of recursively.
 114   std::vector<SDOperand> Worklist;
 115   Worklist.push_back(DAG.getEntryNode());
 116
 117   // Note that we can do this in the IA64 target (scanning forward across token
 118   // chain edges) because no nodes ever get folded across these edges.  On a
 119   // target like X86 which supports load/modify/store operations, this would
 120   // have to be more careful.
 121   while (!Worklist.empty()) {
 122     SDOperand Node = Worklist.back();
 123     Worklist.pop_back();
 124
 125     // Chose from the least deep of the top two nodes.
 126     if (!Worklist.empty() &&
 127         Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
 128       std::swap(Worklist.back(), Node);
 129
 130     if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
 131          Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
 132         CodeGenMap.count(Node)) continue;
 133
 134     for (SDNode::use_iterator UI = Node.Val->use_begin(),
 135          E = Node.Val->use_end(); UI != E; ++UI) {
 136       // Scan the values.  If this use has a value that is a token chain, add it
 137       // to the worklist.
 138       SDNode *User = *UI;
 139       for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
 140         if (User->getValueType(i) == MVT::Other) {
 141           Worklist.push_back(SDOperand(User, i));
 142           break;
 143         }
 144     }
 145
 146     // Finally, legalize this node.
 147     SDOperand Dummy;
 148     Select(Dummy, Node);
 149   }
 150
 151   // Select target instructions for the DAG.
 152   DAG.setRoot(SelectRoot(DAG.getRoot()));
 153   CodeGenMap.clear();
 154   DAG.RemoveDeadNodes();
 155
 156   // Emit machine code to BB.
 157   ScheduleAndEmitDAG(DAG);
 158 }
 159
 160 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
 161   SDNode *N = Op.Val;
 162   SDOperand Chain, Tmp1, Tmp2;
 163   Select(Chain, N->getOperand(0));
 164
 165   Select(Tmp1, N->getOperand(0));
 166   Select(Tmp2, N->getOperand(1));
 167
 168   bool isFP=false;
 169
 170   if(MVT::isFloatingPoint(Tmp1.getValueType()))
 171     isFP=true;
 172
 173   bool isModulus=false; // is it a division or a modulus?
 174   bool isSigned=false;
 175
 176   switch(N->getOpcode()) {
 177     case ISD::FDIV:
 178     case ISD::SDIV:  isModulus=false; isSigned=true;  break;
 179     case ISD::UDIV:  isModulus=false; isSigned=false; break;
 180     case ISD::FREM:
 181     case ISD::SREM:  isModulus=true;  isSigned=true;  break;
 182     case ISD::UREM:  isModulus=true;  isSigned=false; break;
 183   }
 184
 185   // TODO: check for integer divides by powers of 2 (or other simple patterns?)
 186
 187     SDOperand TmpPR, TmpPR2;
 188     SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
 189     SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
 190     SDNode *Result;
 191
 192     // we'll need copies of F0 and F1
 193     SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
 194     SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
 195
 196     // OK, emit some code:
 197
 198     if(!isFP) {
 199       // first, load the inputs into FP regs.
 200       TmpF1 =
 201         SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
 202       Chain = TmpF1.getValue(1);
 203       TmpF2 =
 204         SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
 205       Chain = TmpF2.getValue(1);
 206
 207       // next, convert the inputs to FP
 208       if(isSigned) {
 209         TmpF3 =
 210           SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
 211         Chain = TmpF3.getValue(1);
 212         TmpF4 =
 213           SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
 214         Chain = TmpF4.getValue(1);
 215       } else { // is unsigned
 216         TmpF3 =
 217           SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
 218         Chain = TmpF3.getValue(1);
 219         TmpF4 =
 220           SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
 221         Chain = TmpF4.getValue(1);
 222       }
 223
 224     } else { // this is an FP divide/remainder, so we 'leak' some temp
 225              // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
 226       TmpF3=Tmp1;
 227       TmpF4=Tmp2;
 228     }
 229
 230     // we start by computing an approximate reciprocal (good to 9 bits?)
 231     // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
 232     if(isFP)
 233       TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
 234                                               TmpF3, TmpF4), 0);
 235     else
 236       TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
 237                                               TmpF3, TmpF4), 0);
 238
 239     TmpPR = TmpF5.getValue(1);
 240     Chain = TmpF5.getValue(2);
 241
 242     SDOperand minusB;
 243     if(isModulus) { // for remainders, it'll be handy to have
 244                              // copies of -input_b
 245       minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
 246                   CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
 247       Chain = minusB.getValue(1);
 248     }
 249
 250     SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
 251
 252     TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
 253                                             TmpF4, TmpF5, F1, TmpPR), 0);
 254     Chain = TmpE0.getValue(1);
 255     TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 256                                             TmpF5, TmpE0, TmpF5, TmpPR), 0);
 257     Chain = TmpY1.getValue(1);
 258     TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 259                                             TmpE0, TmpE0, F0, TmpPR), 0);
 260     Chain = TmpE1.getValue(1);
 261     TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 262                                             TmpY1, TmpE1, TmpY1, TmpPR), 0);
 263     Chain = TmpY2.getValue(1);
 264
 265     if(isFP) { // if this is an FP divide, we finish up here and exit early
 266       if(isModulus)
 267         assert(0 && "Sorry, try another FORTRAN compiler.");
 268
 269       SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
 270
 271       TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 272                                               TmpE1, TmpE1, F0, TmpPR), 0);
 273       Chain = TmpE2.getValue(1);
 274       TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 275                                               TmpY2, TmpE2, TmpY2, TmpPR), 0);
 276       Chain = TmpY3.getValue(1);
 277       TmpQ0 =
 278         SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
 279                                         Tmp1, TmpY3, F0, TmpPR), 0);
 280       Chain = TmpQ0.getValue(1);
 281       TmpR0 =
 282         SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
 283                                         Tmp2, TmpQ0, Tmp1, TmpPR), 0);
 284       Chain = TmpR0.getValue(1);
 285
 286 // we want Result to have the same target register as the frcpa, so
 287 // we two-address hack it. See the comment "for this to work..." on
 288 // page 48 of Intel application note #245415
 289       Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
 290                                      TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
 291       Chain = SDOperand(Result, 1);
 292       return SDOperand(Result, 0); // XXX: early exit!
 293     } else { // this is *not* an FP divide, so there's a bit left to do:
 294
 295       SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
 296
 297       TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
 298                                               TmpF3, TmpY2, F0, TmpPR), 0);
 299       Chain = TmpQ2.getValue(1);
 300       TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
 301                                               TmpF4, TmpQ2, TmpF3, TmpPR), 0);
 302       Chain = TmpR2.getValue(1);
 303
 304 // we want TmpQ3 to have the same target register as the frcpa? maybe we
 305 // should two-address hack it. See the comment "for this to work..." on page
 306 // 48 of Intel application note #245415
 307       TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
 308                                          TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
 309       Chain = TmpQ3.getValue(1);
 310
 311       // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
 312       // the FPSWA won't be able to help out in the case of large/tiny
 313       // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
 314
 315       if(isSigned)
 316         TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
 317                                                MVT::f64, TmpQ3), 0);
 318       else
 319         TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
 320                                                MVT::f64, TmpQ3), 0);
 321
 322       Chain = TmpQ.getValue(1);
 323
 324       if(isModulus) {
 325         SDOperand FPminusB =
 326           SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
 327         Chain = FPminusB.getValue(1);
 328         SDOperand Remainder =
 329           SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
 330                                           TmpQ, FPminusB, TmpF1), 0);
 331         Chain = Remainder.getValue(1);
 332         Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
 333         Chain = SDOperand(Result, 1);
 334       } else { // just an integer divide
 335         Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
 336         Chain = SDOperand(Result, 1);
 337       }
 338
 339       return SDOperand(Result, 0);
 340     } // wasn't an FP divide
 341 }
 342
 343 // Select - Convert the specified operand from a target-independent to a
 344 // target-specific node if it hasn't already been changed.
 345 void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 346   SDNode *N = Op.Val;
 347   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
 348       N->getOpcode() < IA64ISD::FIRST_NUMBER) {
 349     Result = Op;
 350     return;   // Already selected.
 351   }
 352
 353   // If this has already been converted, use it.
 354   std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
 355   if (CGMI != CodeGenMap.end()) {
 356     Result = CGMI->second;
 357     return;
 358   }
 359
 360   switch (N->getOpcode()) {
 361   default: break;
 362
 363   case IA64ISD::BRCALL: { // XXX: this is also a hack!
 364     SDOperand Chain;
 365     SDOperand InFlag;  // Null incoming flag value.
 366
 367     Select(Chain, N->getOperand(0));
 368     if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
 369       Select(InFlag, N->getOperand(2));
 370
 371     unsigned CallOpcode;
 372     SDOperand CallOperand;
 373
 374     // if we can call directly, do so
 375     if (GlobalAddressSDNode *GASD =
 376       dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
 377       CallOpcode = IA64::BRCALL_IPREL_GA;
 378       CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
 379     } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
 380                                          // case for correctness, to avoid
 381                                          // "non-pic code with imm reloc.n
 382                                          // against dynamic symbol" errors
 383              dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
 384     CallOpcode = IA64::BRCALL_IPREL_ES;
 385     CallOperand = N->getOperand(1);
 386   } else {
 387     // otherwise we need to load the function descriptor,
 388     // load the branch target (function)'s entry point and GP,
 389     // branch (call) then restore the GP
 390     SDOperand FnDescriptor;
 391     Select(FnDescriptor, N->getOperand(1));
 392
 393     // load the branch target's entry point [mem] and
 394     // GP value [mem+8]
 395     SDOperand targetEntryPoint=
 396       SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
 397     Chain = targetEntryPoint.getValue(1);
 398     SDOperand targetGPAddr=
 399       SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
 400                     FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
 401     Chain = targetGPAddr.getValue(1);
 402     SDOperand targetGP=
 403       SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
 404     Chain = targetGP.getValue(1);
 405
 406     Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
 407     InFlag = Chain.getValue(1);
 408     Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
 409     InFlag = Chain.getValue(1);
 410
 411     CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
 412     CallOpcode = IA64::BRCALL_INDIRECT;
 413   }
 414
 415    // Finally, once everything is setup, emit the call itself
 416    if(InFlag.Val)
 417      Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
 418                                              CallOperand, InFlag), 0);
 419    else // there might be no arguments
 420      Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
 421                                              CallOperand, Chain), 0);
 422    InFlag = Chain.getValue(1);
 423
 424    std::vector<SDOperand> CallResults;
 425
 426    CallResults.push_back(Chain);
 427    CallResults.push_back(InFlag);
 428
 429    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
 430      CodeGenMap[Op.getValue(i)] = CallResults[i];
 431    Result = CallResults[Op.ResNo];
 432    return;
 433   }
 434
 435   case IA64ISD::GETFD: {
 436     SDOperand Input;
 437     Select(Input, N->getOperand(0));
 438     Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
 439     CodeGenMap[Op] = Result;
 440     return;
 441   }
 442
 443   case ISD::FDIV:
 444   case ISD::SDIV:
 445   case ISD::UDIV:
 446   case ISD::SREM:
 447   case ISD::UREM:
 448     Result = SelectDIV(Op);
 449     return;
 450
 451   case ISD::TargetConstantFP: {
 452     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
 453
 454     if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
 455       Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
 456     } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
 457       Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
 458     } else
 459       assert(0 && "Unexpected FP constant!");
 460     return;
 461   }
 462
 463   case ISD::FrameIndex: { // TODO: reduce creepyness
 464     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 465     if (N->hasOneUse())
 466       Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
 467                                   CurDAG->getTargetFrameIndex(FI, MVT::i64));
 468     else
 469       Result = CodeGenMap[Op] = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
 470                                 CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
 471     return;
 472   }
 473
 474   case ISD::ConstantPool: { // TODO: nuke the constant pool
 475                             //       (ia64 doesn't need one)
 476     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
 477     Constant *C = CP->get();
 478     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
 479                                                   CP->getAlignment());
 480     Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
 481                               CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
 482     return;
 483   }
 484
 485   case ISD::GlobalAddress: {
 486     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
 487     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
 488     SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
 489                                   CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
 490     Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
 491     return;
 492   }
 493
 494 /* XXX  case ISD::ExternalSymbol: {
 495     SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
 496           MVT::i64);
 497     SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
 498                                   CurDAG->getRegister(IA64::r1, MVT::i64), EA);
 499     return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
 500  }
 501 */
 502
 503   case ISD::LOAD:
 504   case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
 505   case ISD::ZEXTLOAD: {
 506     SDOperand Chain, Address;
 507     Select(Chain, N->getOperand(0));
 508     Select(Address, N->getOperand(1));
 509
 510     MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
 511       N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
 512     unsigned Opc;
 513     switch (TypeBeingLoaded) {
 514     default: N->dump(); assert(0 && "Cannot load this type!");
 515     case MVT::i1: { // this is a bool
 516       Opc = IA64::LD1; // first we load a byte, then compare for != 0
 517       if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
 518         Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
 519                     SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
 520                                   CurDAG->getRegister(IA64::r0, MVT::i64),
 521                                   Chain).getValue(Op.ResNo);
 522         return;
 523       }
 524       /* otherwise, we want to load a bool into something bigger: LD1
 525          will do that for us, so we just fall through */
 526     }
 527     case MVT::i8:  Opc = IA64::LD1; break;
 528     case MVT::i16: Opc = IA64::LD2; break;
 529     case MVT::i32: Opc = IA64::LD4; break;
 530     case MVT::i64: Opc = IA64::LD8; break;
 531
 532     case MVT::f32: Opc = IA64::LDF4; break;
 533     case MVT::f64: Opc = IA64::LDF8; break;
 534     }
 535
 536     // TODO: comment this
 537     Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
 538                                 Address, Chain).getValue(Op.ResNo);
 539     return;
 540   }
 541
 542   case ISD::TRUNCSTORE:
 543   case ISD::STORE: {
 544     SDOperand Address, Chain;
 545     Select(Address, N->getOperand(2));
 546     Select(Chain, N->getOperand(0));
 547
 548     unsigned Opc;
 549     if (N->getOpcode() == ISD::STORE) {
 550       switch (N->getOperand(1).getValueType()) {
 551       default: assert(0 && "unknown type in store");
 552       case MVT::i1: { // this is a bool
 553         Opc = IA64::ST1; // we store either 0 or 1 as a byte
 554         // first load zero!
 555         SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
 556         Chain = Initial.getValue(1);
 557         // then load 1 into the same reg iff the predicate to store is 1
 558         SDOperand Tmp;
 559         Select(Tmp, N->getOperand(1));
 560         Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
 561                                               CurDAG->getConstant(1, MVT::i64),
 562                                               Tmp), 0);
 563         Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
 564         return;
 565       }
 566       case MVT::i64: Opc = IA64::ST8;  break;
 567       case MVT::f64: Opc = IA64::STF8; break;
 568       }
 569     } else { //ISD::TRUNCSTORE
 570       switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
 571       default: assert(0 && "unknown type in truncstore");
 572       case MVT::i8:  Opc = IA64::ST1;  break;
 573       case MVT::i16: Opc = IA64::ST2;  break;
 574       case MVT::i32: Opc = IA64::ST4;  break;
 575       case MVT::f32: Opc = IA64::STF4; break;
 576       }
 577     }
 578
 579     SDOperand N1, N2;
 580     Select(N1, N->getOperand(1));
 581     Select(N2, N->getOperand(2));
 582     Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
 583     return;
 584   }
 585
 586   case ISD::BRCOND: {
 587     SDOperand Chain, CC;
 588     Select(Chain, N->getOperand(0));
 589     Select(CC, N->getOperand(1));
 590     MachineBasicBlock *Dest =
 591       cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
 592     //FIXME - we do NOT need long branches all the time
 593     Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
 594                                 CurDAG->getBasicBlock(Dest), Chain);
 595     return;
 596   }
 597
 598   case ISD::CALLSEQ_START:
 599   case ISD::CALLSEQ_END: {
 600     int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
 601     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
 602                        IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
 603     SDOperand N0;
 604     Select(N0, N->getOperand(0));
 605     Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
 606     return;
 607   }
 608
 609   case ISD::BR:
 610                  // FIXME: we don't need long branches all the time!
 611     SDOperand N0;
 612     Select(N0, N->getOperand(0));
 613     Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
 614                                 N->getOperand(1), N0);
 615     return;
 616   }
 617
 618   SelectCode(Result, Op);
 619 }
 620
 621
 622 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
 623 /// into an IA64-specific DAG, ready for instruction scheduling.
 624 ///
 625 FunctionPass
 626 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
 627   return new IA64DAGToDAGISel(TM);
 628 }
 629