lib/Target/X86/X86ISelLowering.h

   1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Chris Lattner and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that X86 uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef X86ISELLOWERING_H
  16 #define X86ISELLOWERING_H
  17
  18 #include "X86Subtarget.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21
  22 namespace llvm {
  23   namespace X86ISD {
  24     // X86 Specific DAG Nodes
  25     enum NodeType {
  26       // Start the numbering where the builtin ops leave off.
  27       FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
  28
  29       /// SHLD, SHRD - Double shift instructions. These correspond to
  30       /// X86::SHLDxx and X86::SHRDxx instructions.
  31       SHLD,
  32       SHRD,
  33
  34       /// FAND - Bitwise logical AND of floating point values. This corresponds
  35       /// to X86::ANDPS or X86::ANDPD.
  36       FAND,
  37
  38       /// FXOR - Bitwise logical XOR of floating point values. This corresponds
  39       /// to X86::XORPS or X86::XORPD.
  40       FXOR,
  41
  42       /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
  43       /// integer source in memory and FP reg result.  This corresponds to the
  44       /// X86::FILD*m instructions. It has three inputs (token chain, address,
  45       /// and source type) and two outputs (FP value and token chain). FILD_FLAG
  46       /// also produces a flag).
  47       FILD,
  48       FILD_FLAG,
  49
  50       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
  51       /// integer destination in memory and a FP reg source.  This corresponds
  52       /// to the X86::FIST*m instructions and the rounding mode change stuff. It
  53       /// has two inputs (token chain and address) and two outputs (int value and
  54       /// token chain).
  55       FP_TO_INT16_IN_MEM,
  56       FP_TO_INT32_IN_MEM,
  57       FP_TO_INT64_IN_MEM,
  58
  59       /// FLD - This instruction implements an extending load to FP stack slots.
  60       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
  61       /// operand, ptr to load from, and a ValueType node indicating the type
  62       /// to load to.
  63       FLD,
  64
  65       /// FST - This instruction implements a truncating store to FP stack
  66       /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
  67       /// chain operand, value to store, address, and a ValueType to store it
  68       /// as.
  69       FST,
  70
  71       /// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
  72       /// which copies from ST(0) to the destination. It takes a chain and writes
  73       /// a RFP result and a chain.
  74       FP_GET_RESULT,
  75
  76       /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
  77       /// which copies the source operand to ST(0). It takes a chain and writes
  78       /// a chain and a flag.
  79       FP_SET_RESULT,
  80
  81       /// CALL/TAILCALL - These operations represent an abstract X86 call
  82       /// instruction, which includes a bunch of information.  In particular the
  83       /// operands of these node are:
  84       ///
  85       ///     #0 - The incoming token chain
  86       ///     #1 - The callee
  87       ///     #2 - The number of arg bytes the caller pushes on the stack.
  88       ///     #3 - The number of arg bytes the callee pops off the stack.
  89       ///     #4 - The value to pass in AL/AX/EAX (optional)
  90       ///     #5 - The value to pass in DL/DX/EDX (optional)
  91       ///
  92       /// The result values of these nodes are:
  93       ///
  94       ///     #0 - The outgoing token chain
  95       ///     #1 - The first register result value (optional)
  96       ///     #2 - The second register result value (optional)
  97       ///
  98       /// The CALL vs TAILCALL distinction boils down to whether the callee is
  99       /// known not to modify the caller's stack frame, as is standard with
 100       /// LLVM.
 101       CALL,
 102       TAILCALL,
 103
 104       /// RDTSC_DAG - This operation implements the lowering for
 105       /// readcyclecounter
 106       RDTSC_DAG,
 107
 108       /// X86 compare and logical compare instructions.
 109       CMP, TEST, COMI, UCOMI,
 110
 111       /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
 112       /// operand produced by a CMP instruction.
 113       SETCC,
 114
 115       /// X86 conditional moves. Operand 1 and operand 2 are the two values
 116       /// to select from (operand 1 is a R/W operand). Operand 3 is the condition
 117       /// code, and operand 4 is the flag operand produced by a CMP or TEST
 118       /// instruction. It also writes a flag result.
 119       CMOV,
 120
 121       /// X86 conditional branches. Operand 1 is the chain operand, operand 2
 122       /// is the block to branch if condition is true, operand 3 is the
 123       /// condition code, and operand 4 is the flag operand produced by a CMP
 124       /// or TEST instruction.
 125       BRCOND,
 126
 127       /// Return with a flag operand. Operand 1 is the chain operand, operand
 128       /// 2 is the number of bytes of stack to pop.
 129       RET_FLAG,
 130
 131       /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
 132       REP_STOS,
 133
 134       /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
 135       REP_MOVS,
 136
 137       /// LOAD_PACK Load a 128-bit packed float / double value. It has the same
 138       /// operands as a normal load.
 139       LOAD_PACK,
 140
 141       /// GlobalBaseReg - On Darwin, this node represents the result of the popl
 142       /// at function entry, used for PIC code.
 143       GlobalBaseReg,
 144
 145       /// TCPWrapper - A wrapper node for TargetConstantPool,
 146       /// TargetExternalSymbol, and TargetGlobalAddress.
 147       Wrapper,
 148
 149       /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
 150       /// have to match the operand type.
 151       S2VEC,
 152
 153       /// ZEXT_S2VEC - SCALAR_TO_VECTOR with zero extension. The destination base
 154       /// does not have to match the operand type.
 155       ZEXT_S2VEC,
 156
 157       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
 158       /// i32, corresponds to X86::PEXTRW.
 159       PEXTRW,
 160
 161       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
 162       /// corresponds to X86::PINSRW.
 163       PINSRW,
 164     };
 165
 166     // X86 specific condition code. These correspond to X86_*_COND in
 167     // X86InstrInfo.td. They must be kept in synch.
 168     enum CondCode {
 169       COND_A  = 0,
 170       COND_AE = 1,
 171       COND_B  = 2,
 172       COND_BE = 3,
 173       COND_E  = 4,
 174       COND_G  = 5,
 175       COND_GE = 6,
 176       COND_L  = 7,
 177       COND_LE = 8,
 178       COND_NE = 9,
 179       COND_NO = 10,
 180       COND_NP = 11,
 181       COND_NS = 12,
 182       COND_O  = 13,
 183       COND_P  = 14,
 184       COND_S  = 15,
 185       COND_INVALID
 186     };
 187   }
 188
 189  /// Define some predicates that are used for node matching.
 190  namespace X86 {
 191    /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
 192    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 193    bool isPSHUFDMask(SDNode *N);
 194
 195    /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
 196    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 197    bool isPSHUFHWMask(SDNode *N);
 198
 199    /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
 200    /// specifies a shuffle of elements that is suitable for input to PSHUFD.
 201    bool isPSHUFLWMask(SDNode *N);
 202
 203    /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
 204    /// specifies a shuffle of elements that is suitable for input to SHUFP*.
 205    bool isSHUFPMask(SDNode *N);
 206
 207    /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
 208    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
 209    bool isMOVLHPSMask(SDNode *N);
 210
 211    /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
 212    /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
 213    bool isMOVHLPSMask(SDNode *N);
 214
 215    /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
 216    /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
 217    bool isMOVLPMask(SDNode *N);
 218
 219    /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
 220    /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}.
 221    bool isMOVHPMask(SDNode *N);
 222
 223    /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
 224    /// specifies a shuffle of elements that is suitable for input to UNPCKL.
 225    bool isUNPCKLMask(SDNode *N);
 226
 227    /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
 228    /// specifies a shuffle of elements that is suitable for input to UNPCKH.
 229    bool isUNPCKHMask(SDNode *N);
 230
 231    /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
 232    /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
 233    /// <0, 0, 1, 1>
 234    bool isUNPCKL_v_undef_Mask(SDNode *N);
 235
 236    /// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand
 237    /// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
 238    bool isMOVSMask(SDNode *N);
 239
 240    /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
 241    /// specifies a splat of a single element.
 242    bool isSplatMask(SDNode *N);
 243
 244    /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
 245    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
 246    /// instructions.
 247    unsigned getShuffleSHUFImmediate(SDNode *N);
 248
 249    /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
 250    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
 251    /// instructions.
 252    unsigned getShufflePSHUFHWImmediate(SDNode *N);
 253
 254    /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
 255    /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
 256    /// instructions.
 257    unsigned getShufflePSHUFLWImmediate(SDNode *N);
 258  }
 259
 260   //===----------------------------------------------------------------------===//
 261   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
 262   class X86TargetLowering : public TargetLowering {
 263     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
 264     int ReturnAddrIndex;              // FrameIndex for return slot.
 265     int BytesToPopOnReturn;           // Number of arg bytes ret should pop.
 266     int BytesCallerReserves;          // Number of arg bytes caller makes.
 267   public:
 268     X86TargetLowering(TargetMachine &TM);
 269
 270     // Return the number of bytes that a function should pop when it returns (in
 271     // addition to the space used by the return address).
 272     //
 273     unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
 274
 275     // Return the number of bytes that the caller reserves for arguments passed
 276     // to this function.
 277     unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
 278
 279     /// LowerOperation - Provide custom lowering hooks for some operations.
 280     ///
 281     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
 282
 283     /// LowerArguments - This hook must be implemented to indicate how we should
 284     /// lower the arguments for the specified function, into the specified DAG.
 285     virtual std::vector<SDOperand>
 286     LowerArguments(Function &F, SelectionDAG &DAG);
 287
 288     /// LowerCallTo - This hook lowers an abstract call to a function into an
 289     /// actual call.
 290     virtual std::pair<SDOperand, SDOperand>
 291     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
 292                 bool isTailCall, SDOperand Callee, ArgListTy &Args,
 293                 SelectionDAG &DAG);
 294
 295     virtual std::pair<SDOperand, SDOperand>
 296     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
 297                             SelectionDAG &DAG);
 298
 299     virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
 300                                                        MachineBasicBlock *MBB);
 301
 302     /// getTargetNodeName - This method returns the name of a target specific
 303     /// DAG node.
 304     virtual const char *getTargetNodeName(unsigned Opcode) const;
 305
 306     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
 307     /// in Mask are known to be either zero or one and return them in the
 308     /// KnownZero/KnownOne bitsets.
 309     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
 310                                                 uint64_t Mask,
 311                                                 uint64_t &KnownZero,
 312                                                 uint64_t &KnownOne,
 313                                                 unsigned Depth = 0) const;
 314
 315     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
 316
 317     std::vector<unsigned>
 318       getRegClassForInlineAsmConstraint(const std::string &Constraint,
 319                                         MVT::ValueType VT) const;
 320
 321     /// isLegalAddressImmediate - Return true if the integer value or
 322     /// GlobalValue can be used as the offset of the target addressing mode.
 323     virtual bool isLegalAddressImmediate(int64_t V) const;
 324     virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
 325
 326     /// isShuffleMaskLegal - Targets can use this to indicate that they only
 327     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
 328     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 329     /// are assumed to be legal.
 330     virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
 331   private:
 332     // C Calling Convention implementation.
 333     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
 334     std::pair<SDOperand, SDOperand>
 335     LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
 336                    bool isTailCall,
 337                    SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
 338
 339     // Fast Calling Convention implementation.
 340     std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
 341     std::pair<SDOperand, SDOperand>
 342     LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
 343                       SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
 344
 345     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
 346     /// make the right decision when generating code for different targets.
 347     const X86Subtarget *Subtarget;
 348
 349     /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
 350     bool X86ScalarSSE;
 351   };
 352 }
 353
 354 #endif    // X86ISELLOWERING_H