1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=atom -instruction-tables < %s | FileCheck %s
13 # CHECK: Instruction Info:
14 # CHECK-NEXT: [1]: #uOps
15 # CHECK-NEXT: [2]: Latency
16 # CHECK-NEXT: [3]: RThroughput
17 # CHECK-NEXT: [4]: MayLoad
18 # CHECK-NEXT: [5]: MayStore
19 # CHECK-NEXT: [6]: HasSideEffects (U)
21 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
22 # CHECK-NEXT: 1 1 1.00 * movbew %cx, (%rax)
23 # CHECK-NEXT: 1 1 1.00 * movbew (%rax), %cx
24 # CHECK-NEXT: 1 1 1.00 * movbel %ecx, (%rax)
25 # CHECK-NEXT: 1 1 1.00 * movbel (%rax), %ecx
26 # CHECK-NEXT: 1 1 1.00 * movbeq %rcx, (%rax)
27 # CHECK-NEXT: 1 1 1.00 * movbeq (%rax), %rcx
30 # CHECK-NEXT: [0] - AtomPort0
31 # CHECK-NEXT: [1] - AtomPort1
33 # CHECK: Resource pressure per iteration:
37 # CHECK: Resource pressure by instruction:
38 # CHECK-NEXT: [0] [1] Instructions:
39 # CHECK-NEXT: 1.00 - movbew %cx, (%rax)
40 # CHECK-NEXT: 1.00 - movbew (%rax), %cx
41 # CHECK-NEXT: 1.00 - movbel %ecx, (%rax)
42 # CHECK-NEXT: 1.00 - movbel (%rax), %ecx
43 # CHECK-NEXT: 1.00 - movbeq %rcx, (%rax)
44 # CHECK-NEXT: 1.00 - movbeq (%rax), %rcx