test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
   3
   4 # The SBB does not depend on the value of register EAX. That means, it doesn't
   5 # have to wait for the IMUL to write-back on EAX. However, it still depends on
   6 # the ADD for EFLAGS.
   7
   8 imul %edx, %eax
   9 add %edx, %edx
  10 sbb %eax, %eax
  11
  12 # CHECK:      Iterations:        1500
  13 # CHECK-NEXT: Instructions:      4500
  14 # CHECK-NEXT: Total Cycles:      7503
  15 # CHECK-NEXT: Total uOps:        6000
  16
  17 # CHECK:      Dispatch Width:    4
  18 # CHECK-NEXT: uOps Per Cycle:    0.80
  19 # CHECK-NEXT: IPC:               0.60
  20 # CHECK-NEXT: Block RThroughput: 1.0
  21
  22 # CHECK:      Instruction Info:
  23 # CHECK-NEXT: [1]: #uOps
  24 # CHECK-NEXT: [2]: Latency
  25 # CHECK-NEXT: [3]: RThroughput
  26 # CHECK-NEXT: [4]: MayLoad
  27 # CHECK-NEXT: [5]: MayStore
  28 # CHECK-NEXT: [6]: HasSideEffects (U)
  29
  30 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  31 # CHECK-NEXT:  1      3     1.00                        imull   %edx, %eax
  32 # CHECK-NEXT:  1      1     0.33                        addl    %edx, %edx
  33 # CHECK-NEXT:  2      2     0.67                        sbbl    %eax, %eax
  34
  35 # CHECK:      Resources:
  36 # CHECK-NEXT: [0]   - SBDivider
  37 # CHECK-NEXT: [1]   - SBFPDivider
  38 # CHECK-NEXT: [2]   - SBPort0
  39 # CHECK-NEXT: [3]   - SBPort1
  40 # CHECK-NEXT: [4]   - SBPort4
  41 # CHECK-NEXT: [5]   - SBPort5
  42 # CHECK-NEXT: [6.0] - SBPort23
  43 # CHECK-NEXT: [6.1] - SBPort23
  44
  45 # CHECK:      Resource pressure per iteration:
  46 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
  47 # CHECK-NEXT:  -      -     1.33   1.33    -     1.33    -      -
  48
  49 # CHECK:      Resource pressure by instruction:
  50 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
  51 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     imull     %edx, %eax
  52 # CHECK-NEXT:  -      -     0.33   0.33    -     0.34    -      -     addl      %edx, %edx
  53 # CHECK-NEXT:  -      -     1.00    -      -     1.00    -      -     sbbl      %eax, %eax
  54
  55 # CHECK:      Timeline view:
  56 # CHECK-NEXT:                     01234567
  57 # CHECK-NEXT: Index     0123456789
  58
  59 # CHECK:      [0,0]     DeeeER    .    . .   imull      %edx, %eax
  60 # CHECK-NEXT: [0,1]     DeE--R    .    . .   addl       %edx, %edx
  61 # CHECK-NEXT: [0,2]     D===eeER  .    . .   sbbl       %eax, %eax
  62 # CHECK-NEXT: [1,0]     .D====eeeER    . .   imull      %edx, %eax
  63 # CHECK-NEXT: [1,1]     .DeE------R    . .   addl       %edx, %edx
  64 # CHECK-NEXT: [1,2]     .D=======eeER  . .   sbbl       %eax, %eax
  65 # CHECK-NEXT: [2,0]     . D========eeeER .   imull      %edx, %eax
  66 # CHECK-NEXT: [2,1]     . DeE----------R .   addl       %edx, %edx
  67 # CHECK-NEXT: [2,2]     . D===========eeER   sbbl       %eax, %eax
  68
  69 # CHECK:      Average Wait times (based on the timeline view):
  70 # CHECK-NEXT: [0]: Executions
  71 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  72 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  73 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  74
  75 # CHECK:            [0]    [1]    [2]    [3]
  76 # CHECK-NEXT: 0.     3     5.0    0.3    0.0       imull        %edx, %eax
  77 # CHECK-NEXT: 1.     3     1.0    0.3    6.0       addl %edx, %edx
  78 # CHECK-NEXT: 2.     3     8.0    0.0    0.0       sbbl %eax, %eax